kds@intelca.UUCP (Ken Shoemaker) (01/18/84)
well people, I remember seeing some requests for information about this
thing a little bit ago, and being that this article appeared in the
Nov/Dec Solutions magazine (an Intel publication <- caveat) I thought
I would put this here for your information (please no flames if it
appears a little bit "hypey" is that a word?)
The bus itself was "reviewed" by 17 firms, who are:
Altos Computer Systems, Advanced Micro Devices, CII-Bull, DIAB,
Foxboro, Hewlett-Packard, Intersil, ICL, Kienzle, Matra, Mupac Corp.,
NCR, Nixdorf Computers, Prime, Siemens, Tektronix and Zilog.
In addition, "55 or so" members of the Multibus manufacturer's group
are committed to support the Multibus II architecture.
I will repeat the last paragraph here for those that don't want to wait:
Copies of the bus specification are now available at a cost of $25 each.
A bus data book is available at no charge.
(the address on the reader service card is:
Intel Corp.
SC6-714
3065 Bowers Ave.
Santa Clara, Ca. 05051
)
------------
Five Seperate Buses
The Multibus II architecture is composed of five seperate buses. They are:
o A 32-bit wide 10 MHz synchronous Parallel System Bus (iPSB) which can
operate at 40 megabytes per second in burst mode. It provides all data
movement and inter-processor communications functions. Being general purpose
in nature, the iPSB bus also supports arbitration, execution and I/O data
movement as well as board configuration support.
It supports four address spaces: a 32-bit wide memory address space;
a 16-bit I/O address space; a 16- or 32-bit message address space; and a
16-bit interconnect address space.
o A 12-MHz Local Bus Extension (iLBX II) providing arbitration-free local
memory expansion up to 64 megabytes. It supports 8-, 16- and 32-bit
processors, and up to six agents or boards.
The iLBX bus provides a 48 megabyte per second bandwidth path to the
processor's memory resources. It includes advanced feature like pipelining and
block transfers of data for more efficient use of the execution bus.
o A 2 MHz Serial System Bus (iSSB) that executes the message passing functions
of the iPSB with a low cost serial interconnect.
Where the iPSB runs at 10 MHz on a 32-bit wide path, the iSSB runs at 2 MHz
on a 1-bit wide path, or roughly two orders of magnitude less. The cost,
likewise, is considerably less.
o A Multichannel DMA (Direct Memory Access) I/O Bus, which is carried over from
the Multibus I architecture. It solves the problem of high speed I/O data
to and from physically distributed custom peripherals such as mass
storage devices and graphics display systems.
The multichannel bus provides a standardized I/O interface with full-speed
operation at up to 15 meters with an asynchronous protocol. It supports up to
16 devices, both 8- and 16-bit, and provides 16 megabyte memory or register
address space per device.
o An iSBX I/O expansion bus, also a carryover from the Multibus I architecture.
It allows incremental on-board system expansion through the use of small
iSBX Multi-module boards.
All iSBX boards allow system expansion without the added cost of another
full expansion board. It allows users to customize their single board
computers to individual applications in response to the latest VLSI technology.
The "open systems" approach
This "open systems" approach helps protect OEMs from the rapid
obsolencence inherent in the avalanche of new microcomputer technology,
especially VLSI.
Because each Multibus II interface is compatible with others, it is in general
simple a matter of choosing the appropriate bus or combination to fit the
needs of a particular application. This means that designers can reconfigure
the system as new requirements arise, or as VLSI developments lead to
improvements in microprocessor technology.
Likewise, Multibus I users can upgrade to multibus II architecture as their
needs grow to 32-bit capabilities, or as their 16-bit systems need more
sophisticated multiprocessing capabilities.
Riding the Technology Wave
The Multibus II message passing protocol is a significant contribution to
multiprocessing. Standardization of the intermodule communication
interface will allow it to be driven into VLSI as well.
The uniform software interface allows users to ride the wave of technology
without having to rewrite their software with every hardware change. This
standardized interface can be driven into VLSI. The Multibus II architecture
will include support devices built expecially for this function.
The Multibus II architecture uses the popular two-piece DIN connector, part
of the Eurocard mechanical standard. The 96-pin version used by Intel
is noted for exceptional reliability and is available from a number of
sources.
It also takes advantage of modular board sizing offered by the Eurocard
standard in specifying two form factors: a 233x220mm size for most
applications and a 100x220mm size for lower cost. Systems may be built
with either the smaller or larger sizes, or the two may be mixed and
matched in the same card cage.
Copies of the bus specification are now available at a cost of $25 each.
A bus data book is avaliable at no charge.
-------------
MULTIBUS, MULTIMODULE, iLBX, iPSB, iSBX, MULTICHANNEL are trademarks of Intel
--
Ken Shoemaker, Intel, Santa Clara, Ca.
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