hull@hao.UUCP (Howard Hull) (02/02/84)
:-<> Extracted (with a pick-axe) and paraphrased (in third person)
from IEEE Micro, p.4, a discussion concerning microprocessor and
microcomputer-based system performance between James Isaak and
Hubert Kirrmann, sees the latter writing something similar to this:
~The most important factor is which part of the Program Counter
is accessible to the outside world, that is, which part of it
comes out of the processor chip -- it tells exactly how much
one can address without external hardware. And it is a good
measure of the processor's addressing capabilities.
It is proposed that processors be classified according to both
the size of their accessible address path and the size of their
data path. Also since multiplexing affects [e.g., reduces]
performance by about 25 percent, it is proposed that when
describing processors the use of a slash (/) to indicate that
the address and data paths are multiplexed and a plus sign (+) to
show that the address and data paths are separate is appropriate.
The 68000 would be a 24+16 processor, for example, and the 8086
would be a 20/16 processor. This tells more about a processor
than, say, "16/32-bit architecture" or, "complete 32-bit virtual
memory performance." to wit:
Zilog/Rockwell/National Intel Motorola/DEC
Z80 16+8 8080A 16+8 6800 16+8
6502 16+8 8085A 16/8 6809 16+8
6512 16+8 8088 20/8 MC68008 20+8
Z8002 16/16 8086 20/16 LSI11/23+ 22/16
Z8001 23/16 80186 20/16 MC68000 23+16
NS16032 24/16 IAPX432 24//16 MC68010 23+16
NS32032 24/32 80286 24+16 MC68020 32+32
Z80000 32/32
The double slash for the IAPX432 means that the address is
transmitted in two parts.~
[Note that I have expanded, altered, and somewhat shuffled the above
tabulation, (for one thing, I reduced the 68000 and 68010 from 24 to
23 address bits pinned out) thus any slurs, unintentional or otherwise,
that may have been in the reply by Kirrmann have been replaced by mine,
likewise unintentional or otherwise!] :-|
Howard Hull
{ucbvax!hplabs | allegra!nbires | decvax!kpno | harpo!seismo | ihnp4!kpno}
!hao!hullkds@intelca.UUCP (Ken Shoemaker) (02/03/84)
I feel compelled to respond to this note, I hope that what I say
makes sense...
Also since multiplexing affects [e.g., reduces]
performance by about 25 percent, it is proposed that when
describing processors the use of a slash (/) to indicate that
the address and data paths are multiplexed and a plus sign (+) to
show that the address and data paths are separate is appropriate.
This is true only if the address time and data times on the bus overlap.
For something like a 68000 this is not true, address information does
not become available until after a bus cycle has started, well after
the data access of the previous bus cycle has completed. Since the address
and data times DO NOT overlap, no performance gain is achieved...It still
takes the 68000 at least 4 clock cycles to access anything, exactly
as it takes the 8086 at least 4 clock cycles, even though the 68000 has
a non-multiplexed bus and the 8086 has a multiplexed bus. The 286
(non-multiplexed address and data), on the other hand
starts another memory access BEFORE the end of the previous
bus cycle, thus allowing improved performance by overlapping
the memory access times between two bus cycles. To realize the performance
improvement you need to interleve memories (or you could also play around
with select circuitry) which the 8207 DRAM controller automatically does
for you.
[Note that I have expanded, altered, and somewhat shuffled the above
tabulation, (for one thing, I reduced the 68000 and 68010 from 24 to
23 address bits pinned out) thus any slurs, unintentional or otherwise,
The 24th address bit would be a byte selection, so there are still 24
address lines selecting bytes (8 bit), 23 address lines selecting words
(16 bit).
--
Ken Shoemaker, Intel, Santa Clara, Ca.
{pur-ee,hplabs,ucbvax!amd70,ogcvax!omsvax}!intelca!kds