GUBBINS@RADC-TOPS20.ARPA (02/17/84)
From: Gern <GUBBINS@RADC-TOPS20.ARPA> As per SMITH prodding, I have examined the concept of uprating my 3 channel 2 I/O port desing to 6 channel, 4 I/O port design. I thought I could pull it off using 3 less chips (no longer need to multiplex I/O) at a cost of $10 more. A patch on my current, stable working 3 channel design indicates that just one buffer now needed on an address line so as to not blow IEEE-696 spec of the new design blows up the PSG chips timming by 10nsec yielding it don't work no more without adding I/O wait circuitry which I have been trying to avoid (note use of run-on sentance to match my run-on thoughts) When I have some time soon I will look at everything again and try to arrive at once again an optimal design and start work on a PC layout and a new prototype , as I don't want to touch my current working 3 channel board. I thought I was cutting my timming kinda fine, but 10 nsec??? Wish me luck. Cheers, Gern -------
mzp@uicsg.UUCP (02/22/84)
#R:sri-arpa:-1669900:uicsg:7600008:000:416 uicsg!mzp Feb 21 13:33:00 1984 I wish you much luck. I just went through the rather harrowing experience of trying to interface one PSG to a 5.3MHz 8086. Those chips are so SLOW! Experimentation with the number of wait states and data setup time showed that their specs are fairly accurate (they know that they're slow). So be careful and watch out for transient errors, because PSG's are really unreliable on the fringe. Mark Papamarcos