Seiler@MIT-XX.ARPA (02/29/84)
From: Larry Seiler <Seiler@MIT-XX.ARPA>
Another entry (apparently) in the 32 bit microprocessor sweepstakes is
the MicroVAX - a single chip implementation of the DEC VAX architecture.
I heard about it at a talk at MIT yesterday, which was a repeat of a talk
given at the International Solid State Circuits Conference recently.
The chip has 32 multiplexed address and data lines (32/32) and has an
external interface pretty much like any other microprocessor. It has
full VAX memory management on chip, as well as an interrupt controller and
clock generator. The datapath is 32 bits wide, of course, and has (among
other goodies) a full barrel shifter. External clock is 40MHz, internal
microcycle is 200ns, and the memory cycle time is 400ns.
The chip implements all of the VAX addressing modes, but doesn't directly
implement all instructions or datatypes. Stuff like packed decimal operations
are simulated, with a little bit of microcode assist. Floating point
operations are either simulated in assembly code or are performed in a
separate floating point chip (still being designed). Estimates derived from
a variety of VAX programs suggest that the chip directly implements 98.1%
of executed instructions. Performance is estimated to be equivalent to
a VAX 11/780.
The fly in the ointment is that DEC has not announced in what forms the chip
will be sold, eg, whether you can buy just the chip, or when you can buy it
in any form. But the chip has been fabricated and is being debugged, so it
shouldn't be too awfully long before it will be available in some form. Lots
of people are asking if it's worth waiting for the 68020 or the 16032/32032.
Do you think that the MicroVAX chip is worth waiting for?
Larry Seiler
PS - I have worked for DEC (for what it's worth), but all information in
this message is from the talk given at MIT.
-------SHahn@SUMEX-AIM.ARPA (03/01/84)
From: Sam Hahn <SHahn@SUMEX-AIM.ARPA> On Monday afternoon, I happened to stray into a room at Stanford where someone from DEC was giving a presentation on a 5-chip implementation of the VAX architecture. Performance is very close to the chip described by Larry Seiler, with roughly the same limitations on instruction set and datatypes. Much is in microcode ROM. An optional FPA chip is available. Impressions were that the 5-chip group and the 1-chip group were highly competitive but parallel, and generated working versions within days of each other (2 days, I think he said). Interesting, but not tremendously so until we find out what DEC intends to do with these new implementations. The performance claimed was very, very close to that of the 780, within <10%, it appeared, across categories of cache hits, arithmetic, move, and branch instructions (from what I remember). DEC doesn't yet have any yield figures, since these chips are so new. P.S. This is all from organic memory (mine), which I've never claimed was infallible. I've probably missed a lot, but you'll probably be reading about this pretty soon. -------
WLIM@MIT-XX.ARPA (03/01/84)
From: Willie Lim <WLIM@MIT-XX.ARPA> I was in the MicroVAX talk at MIT. I am particularly interested in the FPA (floating point accelerator) chip. It would be nice if that chip is commercially available. Willie -------