A01MES1@NIU.BITNET (Michael Stack) (05/29/91)
(Cross-posted to ASM370 and IBM-MAIN - sorry about duplicates.)
I had no idea there are so many old f*rts on ASM370. Many of you
may thus remember one of the more interesting problems encountered on
that rare bird, the IBM 360/65. It was discovered by the University
of Waterloo; it seems that WATFOR (or ...FIV) was designed to trap
certain problems by causing an interrupt through branching to an odd
address, then analyzing the PI old PSW - my memory of this is vague,
as is my memory of nearly everything that happened fifteen years ago.
In any case, it seems that the 360/65 had the odd habit of presenting
an interrupt address in the PIOPSW which was eight bytes too low.
Naturally, WATxxx had a difficult time analyzing the problems which
led to this, so Waterloo called on SHARE to submit a Requirement to
IBM to correct the microcode in the 360/65.
I have in front of me a copy of a letter from Mike Armstrong, then
of the University of Rochester, to Jerry Feinman, now and for ever
Blue (BTW, for those who don't know Jerry, he currently "owns" MVS).
I won't quote from Mike's letter (which was submitted to, but never
published in, the SHARE Secretary's Distribution); it was a lengthy
explanation of just exactly what he thought of IBM's response to the
resolution, documented by quotes from IBM manuals. You may, however,
be interested in the resolution and IBM's response. It was submitted
by the OS/MVT-MFT Project of the Basic Systems Division of SHARE, one
R.P. Rannie, Project Manager; heaven knows who responded for Blue.
REQUIREMENT:
IBM should correct the hardware malfunction on the 360/65. The
problem occurs when a "branch to *+1" instruction is executed.
The resulting program check old PSW address is 8 bytes too low.
This problem has been acknowledged by IBM to be a hardware
problem. It is a problem in the sense that the performance of
the hardware is not in accordance with that described in the
manual on Principles of Operation.
RESPONSE: Rejected.
COMMENT: The problem referred to by the resolution occurs as
a result of his trying to incorrectly use a Branch
instruction; e.g., the low order bit of a branch
address must be zero (GA22-6821-8, Principles of
Operation, page 17). Because the hardware imple-
mentation of the system architecture may be different
in the various models, the imporper (sic) use of an
instruction may not necessarily yield the same result
between models. This is not a violation of the
architecture since properly written instructions
execute correctly. We see no reason to make hardware
changes to permit the incorrect use of a system.
This can't be the first time that "broken as designed" and "catch 22"
combined in such a manner, but it may never have been done better.
Michael Stack
Northern Illinois University Internet: A01MES1@MVS.NIU.EDU
Computer Systems and Operations Bitnet: A01MES1@NIU
DeKalb, IL 60115-2854 Earnet: 815-753-9447