joepwro@ihopa.UUCP (Joe Wroblewski) (03/07/84)
There has been a lot of talk lately about the 68020. I understand that it is suppose to be a "complete" 32-bit implementation with many new insturctions. Also it is suppose to have an automatic coprocessor interface and an on-chip instruction cache. Could somebody please post a detailed description inlcuding the following: 1. How many bits is the data bus? 2. How many bits is the address bus? 3. Can the ALU handle 32-bit operands? 4. How will it be packaged? 5. What will its maximum clock speed be? 6. When will it be available? 7. Any other important facts. Thanks for reading. Joe P. Wro.
gnu@sun.uucp (John Gilmore) (03/10/84)
Anyone who really knows the details on the 68020, and posts them, will be in violation of their trade secrets agreement with Motorola. However some info is public. 1. How many bits is the data bus? 32 2. How many bits is the address bus? 32 3. Can the ALU handle 32-bit operands? Yes. Shifts are much faster, too. 4. How will it be packaged? In a pin-grid package -- roughly 100 pins. 5. What will its maximum clock speed be? Hard to tell. Early on, roughly the same as today's 68000's. Later, better. 6. When will it be available? Good question -- and vitally important to their position in the 32-bit market. I think they learned this with the 8086/68000 battle though, so there's hope for it coming soon. 7. Any other important facts. There is a coprocessor interface and an on-chip instruction cache. The coprocessor interface is truly general, unlike those on the 8086, 80286, or 16032/32032 -- the instruction decoding is done by the coprocessor, not by the CPU, so you can make a custom coprocessor (out of TTL or with a custom chip) and it will be part of the instruction set. The coprocessor has full access to the CPU registers, effective address calculations, condition codes, etc. On machines with no coprocessor, the instructions cause a trap and can be simulated in software. The cache makes things run faster, and also decreases memory bus utilization. The 68000/68010 keep the bus busy well over 90% of the time. In the 68020 they are shooting for more like 50%. This would make it feasible to put two 68020's on the same memory and make a tightly coupled multiprocessor system without losing too much to bus conflicts. The instruction set is enhanced to include 32-bit quantities everywhere, including multiply/divide, displacements in branches and indexed addressing modes, etc. Many new addressing modes are planned, including indirect thru memory as well as scaled index. A floating point coprocessor is planned -- looks to be VERY fast and complete, better than anything else on the market -- as well as a decent memory management unit. These chips will appear after the 68020, not at the same time. This information comes from "MC68020 Product Preview" and "MC68881 Product Preview" from 1982. They are about 4 pages each and were part of the press kit Motorola released when they announced the 68010 and 68020.
KSPROUL@RUTGERS.ARPA (03/10/84)
The 68020 is a REAL 32 bit computer, it will have: 32 bit data bus.. 32 bit address bus.. and eventually be up to 16mhz.. as far as the package, I dont know,,, Keith Sproul Ksproul@Rutgers.arpa -------