zeeff@b-tech.UUCP (Jon Zeeff) (06/13/88)
In article <691@omen.UUCP> caf@omen.UUCP (Chuck Forsberg WA7KGX) writes: > >Replacing the 8250 or 16450 UART ships with the new National NS16550AN >allows Pro-YAM to activate a 16 deep FIFO register. This increases the >allowable interrupt latency by almost an order of magnitude. It is Perhaps Microport could consider supporting this chip in their asy driver. It's probably a simple change. -- Jon Zeeff Branch Technology, uunet!umix!b-tech!zeeff zeeff%b-tech.uucp@umix.cc.umich.edu
rick@pcrat.UUCP (Rick Richardson) (06/21/88)
In article <4540@b-tech.UUCP> zeeff@b-tech.UUCP (Jon Zeeff) writes: >In article <691@omen.UUCP> caf@omen.UUCP (Chuck Forsberg WA7KGX) writes: >> >>Replacing the 8250 or 16450 UART ships with the new National NS16550AN >>allows Pro-YAM to activate a 16 deep FIFO register. This increases the >>allowable interrupt latency by almost an order of magnitude. It is > >Perhaps Microport could consider supporting this chip in their asy driver. >It's probably a simple change. (Sorry, Jack, the cat is out of the bag now! Might as well spill my guts too!) Two of us have been running these parts (the 16550A) since early February in our old AT's running the 'other' UNIX: Venix System V/286. We both have upgraded to 386's, but my 286 is still doing yoeman service handling the Trailblazer at 19.2 with the 16550A -- I could see little reason to upset the stable, solid 286. On the surface the change is a one-liner. Just enable the FIFOs. In fact, before hacking the source I tried this approach by writing a little application that root could execute to turn on the FIFOs. Could have been a net-hero if this had worked!!!!! However, this did not simply work in Venix, because the interrupt service routine tried to process interrupts until the IIR register was equal to "1". With FIFO's enabled, this register will never contain that value. The original test looked like this: while ( (x = inb(IIR)) != 1 ) when it should have (properly) been: while ( ((x = inb(IIR))&1) != 1 ) I don't know if other UNIXes have this same problem. If they do, you'll need source, and/or a desire to squeeze the AND instruction into the existing object code. To enable the FIFO's is really straightforward. You have to decide whether you want to A) minimize interrupt overhead at the expense of allowable interrupt latency, or B) maximize allowable interrupt latency at the expense of interrupt overhead. For the 286, the answer is "B". You want 16 deep FIFOs that trigger as soon as any characters are available. That gives you the most breathing room for sloppy kernel coding in other areas. The 16550A FIFO control register is a write only register at the same address as the 8250 IIR register. Just write a "1" into that register and whammo! the FIFOs are on. -- Rick Richardson, President, PC Research, Inc. (201) 542-3734 (voice, nights) OR (201) 389-8963 (voice, days) uunet!pcrat!rick (UUCP) rick%pcrat.uucp@uunet.uu.net (INTERNET)
karl@sugar.UUCP (Karl Lehenbauer) (06/23/88)
The 16-byte FIFO on the National NS16550AN pin-compatible (right?) replacement for the 8250 and 16450 UARTs looks like just what the doctor ordered to improve the performance of serial communications under Microport and elsewhere. Has anyone tried to enable the FIFO under Microport and/or would someone at Microport try this, make the driver changes if necessary and post the new driver to the BBS? That would be great. -karl -- -- uunet!sugar!karl