plocher%sally@Sun.COM (John Plocher) (05/03/89)
In article <42700010@osiris.cso.uiuc.edu> dpgerdes@osiris.cso.uiuc.edu writes: >>First, as usual, Mr Plocher is correct in that INT 2 is unusable for all >>PC/AT architecture machines (as opposed to PC bus.) INT 2 is used to cascade > Thanks for the information. I never challenged whether he was correct >or not, but was merely expressing my frustration that every tech person >that has ever made a statement like the above to me has not been able to Let me expand on this thought. First the terminology: INT x = The hardware BUS signal found on many plug in cards PICinput x = The pin on the PIC Intvec x = A location in the software maintained array of ISR addresses ISR = Interrupt Service Routine PIC = Programmable Interrupt Controller When a hardware Interrupt is generated by a board (for e.g., INT 3) the PIC takes the INT 3 hardware signal and (handwaving here) with the help of the CPU generates a call to the routine whose address is found at intvec[ 3 ]. From a low level kernel hackers view of the world like mine (interrupt service routines, interrupt vector tables, and the like) there is no way for a device on an AT BUS to generate a a signal which calls the ISR routine whose address is stored in Intvec[ 2 ]. This is because the input pin on the PIC which would usually be used to generate this action is used instead to add a second PIC chip to the system. In Intel terminology this is called cascading interrupt controller chips. From a mid-level hardware point of view, the BUS SIGNAL (which was called INT 2 on PC and XT systems) gets wired to a pin on the new PIC. This pin is the one which generates calls to the routine at Intvec[ 9 ]. This means that any card which generates a BUS SIGNAL INT 2 ends up activating the Intvec[ 9 ] routine. From a high level view, all you need to do to use cards that have a jumper marked INT 2 is to pronounce it as "Interrupt Nine". This means that you set the jumper to *what is labeled as* INT 2, but set ALL your software to use Intvec[ 9 ]. Very Much Overly Simplified block diagram of the interrupt structure used on AT-style machines. BUS SIGNAL PICinput ---------- ----------- ||| ||| vvv vvv +---------+ INT 2 ------------++| 9 | \ | P | \ INT 10 -----------++| 10 I | \ | C | \ INT 11 -----------++| 11 | \ | 2 | > new in the AT INT 12 -----------++| 12 | / | | / INT 13 -----------++| 13 | / | | / INT 14 -----------++| 14 OUT |++--+ / | | | +---------+ / / +----------------- | CASCADE LINE | \ +---------+ -++| 2 | | | \ INT 3 ------------++| 3 | \ | P | \ INT 4 ------------++| 4 I | \ PCs, XTs, | C | / and ATs INT 5 ------------++| 5 | / | 1 | / INT 6 ------------++| 6 | / | | INT 7 ------------++| 7 OUT |++------>>> To INT pin on CPU | | +---------+ There. A much more in depth answer. Gawd, I hope it is right :-) -John Plocher