WLIM@MIT-XX.ARPA (03/01/84)
From: Willie Lim <WLIM@MIT-XX.ARPA> We are looking for large expandable dual ported memories (those that allow you to read and write simultaneously) for our dataflow supercomputer project. Due to the nature of the problem, we can guarantee that a read and a write to the same location at the same time can never occur (hence arbiters are not needed). Are there any such commercially available chips out there? Is anyone making their own custom VLSI version of such chips? How large (in terms of memory word size) are such chips? All responses will be posted on the net. Thanks. Willie -------
Lannom.WBST@PARC-MAXC.ARPA (03/02/84)
Have you tried Mostek's new MK4501 BiPort FIFO? See their ad in Electronics Feb 23,1984 page 72 Good Luck, Jim Lannom
dollas@uiuccsb.UUCP (03/06/84)
#R:sri-arpa:-1705300:uiuccsb:4400051:000:1999
uiuccsb!dollas Mar 5 07:35:00 1984
To the best of my knowledge there is no such beast as a multiport
memory when one goes down to the hardware-hardware level. The way it
can be faked is by address interleaving, ie rearrangement of the addresses
of the memory requests in such a way that two addresses that need to be
accessed at one time are on different chips. However there is a catch:
you have to know in advance (from the architecture) what kind of
accesses you need to do. For a von Neumann machine it is not that bad
because usually the requests are for consecutive addresses (say, to
load a program, page swapping, etc), in which case one needs only to
make consecutive words be physically separated on the chip level (a
simple example is to have odd/even words separated).
In a dataflow machine the access requests depend of course on the
architecture. In a machine in which virtually all
address combinations can occur it seems to me that the best solution
is to make a multiport (with several ports) memory on the stochastic
model that will yield the fewest conflicts. With any realistic
constraints (cost, complexity, etc) the model will not be perfect
(no conflicts) but you may be surprised at how well such a model can do.
Naturally the smallest the size of each bank that will be 'tied' with a
memory request the better you will do, but with a higher overhead.
It may also be worth to see if your memory accesses are in predetermined
patterns, in which case a solution similar to that discussed in the
previous paragraph may do the trick...
Finally, in terms of multiplexing the addresses I think that it may
be possible to do all the interleaving on the PC board level (thus
saving the delay of multiplexing with active components).
Good Luck!
Apostolos Dollas
Dept. of Comp. Sci.
U. of Illinois
...!pur-ee!uiucdcs!uiuccsb!dollasmason@utcsrgv.UUCP (Dave Mason) (03/07/84)
I think this really belongs in net.arch, so let's move it there (they're
a lonely bunch anyway).
But to the topic:
There are not any large Dual Ported Memories (DPMs) that I am aware of,
but there are some small DPMs that really are 2 accesses at once. The way
they work is (I believe) that there are 2 copies of every peice of data,
and whenever a change is made via one port, it is shadowed over to the other
at some (hopefully soon) convenient time. This way there can be no conflicts
on accessing...much better if you want a synchronous architecture.
Fairchild (probably among others) makes some of these chips..the largest I
know of being something like 32 words x 8 bits. They are intended as register
banks in a CPU, so the speed is probably within your requirements (about 20ns)!
--
{dalcs dciem garfield musocs qucis sask titan trigraph
ubc-vision utzoo watmath allegra cornell decvax decwrl ihnp4 uw-beaver}
!utcsrgv!mason Dave Mason, U. Toronto CSRGBILLW%sri-kl@sri-unix.UUCP (03/09/84)
Don't be silly. You can have a "real" "simple" dual ported memory as long as the memory access speed is twice what either port will require. I believe there was a simple circuit based on this principle published in a recent issue of EDN magazine (in the design ideas portion)... WW
tjt@kobold.UUCP (03/13/84)
Well, I don't know about *large* dual ported memories, but it is quite
common to use dual ported memories for registers in CPU's. It is not
done by address interleaving, but rather by duplicating the memory.
This allows true, independent reads, but any write must be done to
*both* memories. Again, there is a cach in that you need to know what
kind of accesses will be performed. Inside a CPU, the use of multiport
register files is to feed one register as one input to the ALU, another
register to the other ALU input, and then write the result back. The
reads should be simultaneous, but will not overlap with the write.
--
Tom Teixeira, Massachusetts Computer Corporation. Westford MA
...!{ihnp4,harpo,decvax}!masscomp!tjt (617) 692-6200 x275mikezi@shark.UUCP (Mike Ziuchkovski) (03/15/84)
There is a dual port RAM from Synertek (1Kx8) that is being sampled right now. The part number is SY2130 and has an access time of 100 ns. the only conflict is when both ports try to access the same address. 48 pin with separate address and data lines, busy, and interrupt lines. mike ziuchkovski
sasha@uiuccsb.UUCP (04/19/84)
#R:shark:-61800:uiuccsb:4400058:000:527 uiuccsb!sasha Apr 19 12:15:00 1984 /**** uiuccsb:net.micro / shark!mikezi / 10:16 pm Mar 15, 1984 ****/ There is a dual port RAM from Synertek (1Kx8) that is being sampled right now. The part number is SY2130 and has an access time of 100 ns. the only conflict is when both ports try to access the same address. 48 pin with separate address and data lines, busy, and interrupt lines. mike ziuchkovski /* ---------- */ Do you mean that two different addresses can be accessed simulataneuosly? This is kind of unusual. Do you have any idea how is this done?
dont@tekig1.UUCP (Don Taylor) (04/22/84)
X
This is copied, without permission, from 'Digital Design' 4/84, pp 153
'Dual Port Memory Unit
256K ram
The Mc68HC34 is an 8-bit HCMOS dual-port RAM which facilitates
communications between microprocessors with different bus definitions
and clock timings. It allows two processors operating on separate
busses to exchange data. Interrupt registers are the mechanism by
which the processors interrupt each other. The 256 <<<<<<<Kbyte>>>>>>>!
dual-port RAM may be accessed from either microprocessor. The MC68HC34
contains 6 read/write semaphore registers. Price in quantities of
1000 is $25. Motorola, Phoenix, AZ.'
256Kbytes, all in a single 40 pin package, for $25 no less, I'll take 10.
The angle brackets are mine, the 'Kbytes' is theirs, OH I love those typos.
Still, if it is 256Kbits, that is 32Kbytes, this sounds like a STEAL, unless
the price is really $2500, or it is 2.56 bytes.
Don Taylor
tektronix!tekig1!dontWLIM@MIT-XX.ARPA (04/24/84)
From: Willie Lim <WLIM@MIT-XX.ARPA>
The following is a summary of the information I got on large dual
ported memories. All the technical information given are from the
manufacturer's spec. sheets.
1) Use conventional single ported RAM chips that are twice as fast.
2) Use specialized memory chips:
a) Synertek SY2130/SY2131 - Dual ported RAM
----------------------
o 48-pin package
o 100nsec. 1K*8 dual ported RAM
o Synertek's n-channel double poly silicon gate technology
o concurrent access possible if not to the same location
o two arbitration modes available - use on-chip arbitration logic,
or ignore contention
b) MOSTEK MK4501/MK68345 - Dual ported FIFO
---------------------
o 28-pin package
o 120, 150 or 200 nsec. (access time)
o size : 512*9 (expandable to larger memory sizes)
o HCMOS technology
o asynchronous and simultaneous read/write
c) MMI 54/74S419 - FIFO RAM Controller
o to be used with a RAM
o buffer size ranging from 512 to 64K
o arbitration read/write
o 12.5 to 25 MHz. using 25 nsec. RAM
3) Combining 1) and 2a) one can build a four-ported memory.
***********************************
The following are the messages I got in response to my request for
information on large dual ported memories.
Date: Thu 1 Mar 84 13:48:41-EST
From: Larry Seiler <Seiler@MIT-XX.ARPA>
Subject: Re: Large Dual Ported Memories
This may be a dumb idea, but have you considered getting ordinary
memory chips that are twice as fast as you need? You would need
an address mux and a tristate buffer to drive the write data onto
the IO lines, but that's about it. I am currently doing much the
same thing with some standard memory chips, except that mine is
simpler since my write is to the same address as the (preceeding) read.
Enjoy,
Larry
rather than the IEEE formats.
-------
Date: 1 Mar 84 17:04:08 EST
From: Andreas Nowatzyk@CMU-CS-A
Subject: Re: Large Dual Ported Memories
Synertek produces a 1K by 8 dual ported memory with 100ns access time.
The type is SY21D1 and they recently released data sheets. MMI also
claims to have some new DP memories, but their first versions are
hidden as FIFO's.
-- Andreas
Date: Fri, 2 Mar 84 10:04 EST
From: Lannom.WBST@PARC-MAXC.ARPA
Subject: Re: Large Dual Ported Memories
Have you tried Mostek's new MK4501 BiPort FIFO?
See their ad in Electronics Feb 23,1984 page 72
Good Luck,
Jim Lannom
Date: Fri 2 Mar 84 14:49:30-CST
From: John Otken <CC.Otken@UTEXAS-20.ARPA>
Subject: Re: Large Dual Ported Memories
Electronics had an article on a dual ported RAM chip in the last year.
I couldn't find the issue laying around though. John.
-------
(The following message has been edited at the request of the sender.)
Date: 5 Mar 1984 0646 PST
From: Richard B. August <AUGUST@JPL-VLSI>
Subject: Re: Large Dual Ported Memories
REGARDING DUAL-PORT MEMORIES:
The Singer Librascope facility IN GLENDALE,CA HAVE
DONE EXTENSIVE WORK WITH THIS TYPE OF HARDWARE (SPECIFICALLY FOR
USE ON THE TACFILE-CCS PROGRAM).
Phone number for that facility is (213) 244-6541.
REGARDS RAUGUST
------
Date: Sun, 4 Mar 84 13:21:16 est
From: watmath!wateng!bcdoody@Berkeley
Subject: Re: Large Dual Ported Memories
TI (second-sourced by Western Digital) makes the TI(WD)99650
Multiprocessor Interface Device, which is basically a dual-ported 256x8 RAM.
It also contains message registers for inter-processor communication and
READY outputs on both sides. The RAM is accessed indirectly through on-chip
address registers (i.e. address lines don't go into the chip) and simultaneous
accesses from the two sides are arbited internally. It can be expanded
width-wise (to provide 16,24,32 etc bit words).
Hope this was a bit of help.
Brian Doody, Univ. of Waterloo, Elec. Eng., Waterloo, Ont., Can.
Date: 5 Mar 84 19:33:17-PST (Mon)
From: pur-ee!uiucdcs!uiuccsb!dollas@ucb-vax
Subject: Re: Large Dual Ported Memories - (nf)
To the best of my knowledge there is no such beast as a multiport
memory when one goes down to the hardware-hardware level. The way it
can be faked is by address interleaving, ie rearrangement of the addresses
of the memory requests in such a way that two addresses that need to be
accessed at one time are on different chips. However there is a catch:
you have to know in advance (from the architecture) what kind of
accesses you need to do. For a von Neumann machine it is not that bad
because usually the requests are for consecutive addresses (say, to
load a program, page swapping, etc), in which case one needs only to
make consecutive words be physically separated on the chip level (a
simple example is to have odd/even words separated).
In a dataflow machine the access requests depend of course on the
architecture. In a machine in which virtually all
address combinations can occur it seems to me that the best solution
is to make a multiport (with several ports) memory on the stochastic
model that will yield the fewest conflicts. With any realistic
constraints (cost, complexity, etc) the model will not be perfect
(no conflicts) but you may be surprised at how well such a model can do.
Naturally the smallest the size of each bank that will be 'tied' with a
memory request the better you will do, but with a higher overhead.
It may also be worth to see if your memory accesses are in predetermined
patterns, in which case a solution similar to that discussed in the
previous paragraph may do the trick...
Finally, in terms of multiplexing the addresses I think that it may
be possible to do all the interleaving on the PC board level (thus
saving the delay of multiplexing with active components).
Good Luck!
Apostolos Dollas
Dept. of Comp. Sci.
U. of Illinois
...!pur-ee!uiucdcs!uiuccsb!dollas
Date: 8 Mar 1984 17:33-PST
Subject: Re: Large Dual Ported Memories - (nf)
From: BILLW@sri-kl
Don't be silly. You can have a "real" "simple" dual ported
memory as long as the memory access speed is twice what either
port will require. I believe there was a simple circuit
based on this principle published in a recent issue of EDN
magazine (in the design ideas portion)...
WW
Date: 13 Mar 84 6:29:23-PST (Tue)
From: decvax!genrad!grkermit!masscomp!kobold!tjt@ucb-vax
Subject: Re: Large Dual Ported Memories - (nf)
Well, I don't know about *large* dual ported memories, but it is quite
common to use dual ported memories for registers in CPU's. It is not
done by address interleaving, but rather by duplicating the memory.
This allows true, independent reads, but any write must be done to
*both* memories. Again, there is a cach in that you need to know what
kind of accesses will be performed. Inside a CPU, the use of multiport
register files is to feed one register as one input to the ALU, another
register to the other ALU input, and then write the result back. The
reads should be simultaneous, but will not overlap with the write.
--
Tom Teixeira, Massachusetts Computer Corporation. Westford MA
...!{ihnp4,harpo,decvax}!masscomp!tjt (617) 692-6200 x275
Date: 14 Mar 84 13:28:57-PST (Wed)
From: hplabs!tektronix!orca!shark!mikezi@ucb-vax
Subject: Re: Large Dual Ported Memories - (nf)
There is a dual port RAM from Synertek (1Kx8) that is being sampled
right now. The part number is SY2130 and has an access time of 100 ns.
the only conflict is when both ports try to access the same address.
48 pin with separate address and data lines, busy, and interrupt lines.
mike ziuchkovski
Date: 22-Mar-1984 12:02-EST (Thursday)
To: mit-vax!WLIM@MIT-XX.ARPA
Subject: Re: Large Dual Ported Memories - (nf)
I'm not sure where I originally heard of this idea. I have a vague
recollection of this having been patented at one point and that the
patent holder (Data General?) had sued, but I believe lost the suit on
the basis of "prior art". I would be interested in hearing a more
definitive history of this technique.
In any case, in "Introduction to VLSI Systems", by Mead & Conway, the
register array for OM2 (see section 5.9, p 153) uses dual ported
memory. It also latches both the inputs and the outputs to its ALU's.
Tom Teixeira, Massachusetts Computer Corporation. Westford MA
...!{ihnp4,harpo,decvax}!masscomp!tjt (617) 692-6200 x275
P.S. you may also include this message in your summary.
-------