KSPROUL@RUTGERS.ARPA (04/28/84)
The 16 bit 6502 is FINALLY here !!! The Western Design Center Inc of Mesa, Arizona has introduced a 16 bit 6502 compatiable microprocessor. There are two versions of this microprocessor. The W65SC816 is the full version of the chip which can address 16Meg. The W65SC802 is pin-for-pin compatible with the old 6502 and can only access 64K but is FULLY software compatible with the bigger version. The following information is directly out of the WDC W65SC816 data sheet. FEATURS: Advanced CMOS design for low power consumption and increased noise immunity. Single +5 volt supply Emulation mode allows complete hardware and software compatibility with NMOS 6502 24-bit address bus allows access to 16Mbytes of memory space Full 16-bit ALU, Accumulator, Stacp Pointer and Index Registers. Valid Data Address (VDA) and Valid Program Address (VPA) output allows dual cache and cycle steal DMA implementaion Vector Pull (VP\) output indicates when interrupt vectors are being addressed. May be used to implement vectored interrupt design. Separate program and data bank registers allow program segmentaion. New Direct Register allows "zero page" addressing anywhere in the first 64K. 24 addressing modes - 13 original 6502 modes, plus 11 new addressing modes New Wait for Interrupt (WAI) and Stop the Clock (STP) insturcions further reduce power consumption, decrease interrupt latency and allows synchronizaiton with external events. New Co-Processor instrucetion (COP) with associated vector supports co-processor configurations, i.e., floating point processors. New block move ability. W65SC816 Processor Programming Model + - - - - - - - +---------------+---------------+ | 8 bits | 8 bits | 8 bits | + - - - - - - - +---------------+---------------+ + - - - - - - - +---------------+---------------+ | Data Bank Reg | X Register hi | X Register lo | + - - - - - - - +---------------+---------------+ + - - - - - - - +---------------+---------------+ | Data Bank Reg | Y Register hi | Y Register lo | + - - - - - - - +---------------+---------------+ + - - - - - - - +---------------+---------------+ | 00 | Stack Ptr hi | Stack Ptr lo | + - - - - - - - +---------------+---------------+ +---------------+---------------+ | Accumulator A | Accumulator B | +---------------+---------------+ +---------------+---------------+---------------+ | Pgm Bank Reg | Program Ctr Hi| Program Ctr Lo| +---------------+---------------+---------------+ + - - - - - - - +---------------+---------------+ | 00 | Direct Reg Hi | Direct Reg Lo | + - - - - - - - +---------------+---------------+ Status Register (P) - - - - - - - E = Emulation 1 = 6502 N V M X D I Z C | | | | | | | +-- Carry 1 = true | | | | | | +---- Zero 1 = result zero | | | | | +------ IRQ Disable 1 = disable | | | | +-------- Decimal Mode 1 = true | | | +---------- Index reg sel 1 = 8 bit, 0 = 16 bit | | +------------ Memory Select 1 = 8 bit, 0 = 16 bit | +-------------- Overflow 1 = true +---------------- Negative 1 = negative The new instructions are: (These were also on the CMOS version of the 6502) BRA Branch always PLX Pull X PLY Pull Y PHX Push X PHY Push Y STZ Store Zero TRB Test and reset bit TSB Test and set bit New Addressing modes: BIT immediate DEC accumulator direct indirect (No indexing) i.e. LDA (label) all 8 Group I instructions, LDA STA ADC SBC AND ORA EOR CMP INC accumulator JMP Absolute Inexed Indirect JMP (lable,X) New to the W65SC816/W65SC802 Group I instuctions with new addressin modes. Direct indirect long indext with y (all 8 instuctions) Direct Indirect Long (all 8 insturctions) Absoulute Long and Absolute long indexed with X (all 8 instructions) Stack relative (all 8 instructions) Stack relative Indirect indexed Y (all 8 instructions) New push/pull instructions PEA Push effective absoulute address or immediate data word on stack PEI Push effective indirect address or direct daa word on stack PER Push effective Pgm Counter Relative Indirect address or pgm counter relative data word on stack PLB Pull data bank register from stack PLD Pull direct register from stack PHB Push data bank register on stack PHD Push direct register on stack PHK Push program bank register on stack Status register instructions REP Reset status bits defined by immediate byte 1= reset bit 0= do not change SEP Set status bits defined byt immediate byte 1= set bit 0= do not change New register transger instructions TCD Transfer C accumultor to direct register D TDC Transfer Direct Register D to C Accumulator TCS Transfer C accumulator to stack register TSC Transfer Stack register to Accumulator C TXY Transfer X to Y TYX Transfer Y to X XBA exchange B and A SCE Exchange carry bit with emulation bit E New branch jump and return instructions BRL Branch Relative Long Always (-32768 -> +32767) JML Jump indirect Long JMP Jump Absolute Long JSL Jump to subroutine Long (Requires RTL for return) RTL Return from subroutine Long New block move instructions MVN Move block from source (X reg) to destination (y reg) block length of C X & Y are incremented MVP Move block from source (X reg) to destination (y reg) block length of C X & Y are decremented New Co-Processor instuction COP Co-Processor instruction with associated COP vector and Abort Input. New System Control Instructions STP Stop the clock instruction WAI Wait for Interrupt WDM reserved for future systems A NOP at present. You can get samples of this chip from WDC for $95.00 for a 1mhz version They expect to have 4mhz very soon and will eventually go up to 8mhz. The 8mhz version is benchmarked against most of the other popular 16-bit micros, and does very farvorably in a lot of the things they compared. But I thing these comparisons were 'picked'. They included Reg => mem moves, both 8/16 bits and 32 bits. I have one of these beauties orderd and will give more details after I have used it. If anyone has any specfic questions, feel free to ask, but I dont gurantee I know the answers since I dont have a chip yet... Keith Sproul Ksproul@Rutgers.Arpa -------