eugene@wilbur.nas.nasa.gov (Eugene N. Miya) (06/05/90)
From: David K. Kahaner ONRFE [kahaner@xroads.cc.u-tokyo.ac.jp]
Re: Information Processing Society of Japan Symposium on Parallel
Processing '90
5 June 1990
This meeting was held at ETL in Tsukuba 17-19 May 1990. A few of the
papers dealt with material I have already reported, and I expect to
report on some others later, but I felt it was important to make the
titles available as rapidly as possible. The papers were
all given in Japanese, but in the Proceedings a few are printed in
English. We have translated several of the titles so some errors are
possible. Please report these to me for correction.
A copy of the Proceedings is available for 6,000 Yen plus postage from
Information Processing Society of Japan
Hoshina Building
2-4-2 Azabudai
Minato-ku, Tokyo 106, Japan.
PROCEEDINGS OF JOINT SYMPOSIUM ON PARALLEL PROCESSING '90
17-19 May 1990
Electrotechnical Laboratory, Tsukuba, Japan
SESSION T1 - Distributed Memory
Cache Under Program Control in Parallel Processing
Masaki Sato, Masahiro Sowa (Department of Electrical Engineering and
Computer Science Nagoya Institute of Technology, Gokiso, Nagoya 466,
Japan)
Virtual Shared Memory on Loosely-coupled Multiprocessors
Takeshi Yamazaki, Koichi Wada (Institute of Information Science and
Electronics, University of Tsukuba)
Data Transmission Operations on the Parallel Interconnection Model "Cubemat"
Susumu Shibusawa (Department of Computer Science, Gumma University)
SESSION T2 - Distributed Algorithm
Parallel Algorithm for Fast Radix 4 Fourier Transform on an Eight-Neighbor
Processor Array
Kuninobu Tanno (Faculty of Engineering, Yamagata University)
Susumu Horiguti (Faculty of Engineering, Tohoku University)
An Optimal Sorting Algorithm for a Parallel Processor with Multiple Buses
Satoshi Fujita, Masafumi Yamashita, Tadashi Ae (Cluster II, Faculty of
Engineering, Hiroshima University)
The Load Distribution Method Based on the Execution Profile for PIE64
Yasuo Hidaka, Hanpei Koike, Junichi Tatemura, Hidehiko Tanaka
(University of Tokyo, Faculty of Engineering)
SESSION T3 - Synchronization Mechanisms
A Generalized Barrier-type Synchronization Mechanism
Takashi Matsumoto (IBM Research, Tokyo Research Laboratory)
High Speed Static Synchronization without any Additional Waiting
Hiromitsu Takagi, Tadaaki Kawamura, Takaya Arita, Masahiro Sowa
(Department of Electrical Engineering and Computer Science, Nagoya
Institute of Technology)
SESSION T4 - Computation Models
An Algebraic Process Calculus with Asynchronous Communication Mechanism
Kenjiroh Yamanaka (NTT Software Laboratories)
Associative Computation Model: A Computation Mechanism based on
Connectionism
Tatsumi Furuya (Electrotechnical Laboratory
Akio Kokubu (New Media Development Association)
The Parallel Object-oriented Language A'UM-90
Koichi Konishi, Tsutomu Mauruyama, Akihiko Konagaya (C&C Systems
Research Laboratories, NEC Corporation)
Kaoru Yoshida, Takashi Chikayama (Institute for New Generation
Computer Technology)
SESSION A1 - Networks
Implementation and Evaluation of the Interconnection Network of PIE64
Eiichi Takahashi, Hanpei Koike, Hidehiko Tanaka (University of Tokyo,
Faculty of Engineering)
Automatic Detour Path Selection Method on a Hyper Crossbar Network
Teruo Tanaka, Naoki Hamanaka (Central Research laboratory, Hitachi Ltd.)
3-D Optical Interconnection Networks
Shigeru Kawai (C&C Information Technology Research Laboratories, NEC
Corporation)
SESSION A2 - Control Data Flow
The Organization of Global Memory for the Parallel Processing System -Harray-
Hayato Yamana, Hiroshi Katayama, Yoshiro Kusano, Yoichi Muraoka (School
of Science and Engineering, Waseda University)
Processor Optimization and Load Control in Datarol Architecture
Kouji Sonoda, Tetsuro Ueda, Rinichiro Taniguchi, Makoto Amamiya
(Department of Information Systems, Graduate School of Engineering
Sciences, Kyushu University)
Architecture and Design of the CP Parallel Computer
Vinod Sharma, Kouji Yamada, Masahiro Sowa (Nagoya Institute of
Technology, Gokiso-cho, Showa-ku, Nagoya 466, Japan)
SESSION A3 - Symbolic Processing Machines
Architecture of SDC, The Super Database Computer
S. Hirano, M. Harada, M. Nakamura, W. yang, M. Kitsuregawa, M.
Takagi (Institute of Industrial Science, University of Tokyo)
T. Ogawa (Ricoh)
Architecture of PIM/m Processor Element
Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima (Mitsubishi
Electric Corporation)
Associative Multiprocessor IXM2
T. Higuchi, T. Furuya, K. Handa, A. Kokubu (Electrotechnical Laboratory)
SESSION A4 - Data Flow (1)
A Dataflow Single Chip Processor EMC-R Design Principles and
Implementation
Yuetsu Kodama, Shunichi Sakai, Yoshinori Yamaguchi (Electrotechnical
Laboratory)
Architecture of the Data Driven Computer "EDDEN"
Hiroki Miura, Masaki Kawaguchi, Kazuyuki Tanaka, Hideki Ohashi,
Masahisa Shimizu, Noriyuki Mori (Sanyo Electric Co., Ltd.)
SESSION A5 - Data Flow (2)
Architecture of a Prototype Hybrid-dataflow Processor
Kei Hiraki (IBM T.J. Watson Research Center and Electrotechnical
Lab.)
Architecture of the Macro-dataflow Computer CODA
Kenji Toda, Kenji Nishida, Yoshinobu Ochibori, Toshio Shimada
(Electrotechnical Laboratory)
Hardware Design of the Macro-dataflow Computer CODA
Kenji Nishida, Kenji Toda, Yoshinobu Uchibori, Toshio Shimada
(Electrotechnical Laboratory)
SESSION A6 - Architecture
Configuration and Performance Evaluation of a Vector Processor Based on a
Streaming/FIFO Architecture
Tetsuo Hironaka, Keizou Okazaki, Kazuaki Murakami, Shinji Tomita
(Interdisciplinary Graduate School of Engineering Sciences,
Kyushu University)
A Hybrid Parallel Architecture
Takashi Kan, Hiroyuki Miyata, Tetsuaki Isonishi, Akira Iwase
(Information Systems and Electronics Development Laboratory,
Mitsubishi Electric Corporation)
Akira Maeda, Kazunori Sekido, Atsushi Inoue (Information Systems
Laboratory, Toshiba Corporation)
Processor Array QCDPAX and the Debugger for Parallel Programming
Tomonori Shirakawa, Tsutomu Hoshino (Institute of Engineering
Mechanics, University of Tsukuba)
Yoichi Iwsaki, Kazuyuki Kanaya, Tomoteru Yoshie (Institute of
Physics, University of Tsukuba)
Yoshio Oyanagi (Institute of Information Sciences, University of
Tsukuba)
Shingo Ichii (KEK, National Laboratory for High Energy Physics)
Toshio Kawai (Department of Physics, Keio University)
SESSION S1 - Programming Environments
A Distributed Processing System and an Environment for the Cooperative Model
"Cellula"
Norihiko Yoshida, Toshihiko Shimokawa (Kyushu University)
Shuji Narazaki (NTT)
Dataflow Program Developing Environment for the Parallel Processing System -
Harray
Toshiaki Yasue, Jun Kohdate, Hayato Yamana, Yoichi Muraoka
(School of Science and Engineering, Waseda University)
Multiprocessor Real-time Unix Mustard and its Software Development Environment
Shunichi Hiroya, Takeshi Momoi, Toshio Miyachi (C&C Common
Software Development Laboratory, NEC Corporation)
SESSION S2 - Programming Support Methods
Deriving Inductive Properties of Recursive Programs based on Least-fixedpoint
Computation
Satoshi Ono, Mizuhito Ogawa, Yukio Tsuruoka (NTT Software
Laboratories)
The Parallel Programming Language Cable, and Visualization Facility for
Process Communications in Cable
Kazuyuki Yoshida, Kouichi Utsumiya, Kazuyoshi Korida, Kazuhiro Goto,
Tetsuya Harada (Faculty of Engineering, Oita University)
Parallel Programming of Searching Problems in Committed-Choice Parallel Logic
Programming Languages - An Extension of Layered Stream Programming
Yuji Matsumoto (Kyoto University)
Akira Okumura (ICOT)
SESSION S3 - Language Processing Systems
Generation Scavenging GC on Distributed Memory Parallel Computers
Hanpei Koike, Hidehiko Tanaka (University of Tokyo, Faculty of
Engineering)
Improvements in Compiling Procedures for the KL1 - Parallel Logic Language
K. Hirano (Social Science Laboratory, Fujitsu Ltd.)
A. Goto (New Generation Computer Technology Development Organization)
SESSION S4 - Data Driven Languages
Programming System and Performance Evaluation of AMP
Noriyasu Yamamoto, Masatoshi Hotta, Rinichiro Taniguchi, Makoto
Amamiya (Department of Information Systems, Graduate School of
Engineering Sciences, Kyushu University)
Implementation of the Dataflow Parallel Language DFCII
Satoshi Sekiguchi, Toshio Shimada, Kei Hiraki (Electrotechnical
Laboratory)
An Implementation of a Datarol Program on an MIMD Computer
Eiichi Takahashi, Rinichiro Taniguchi, Makoto Amamiya (Graduate
School of Engineering Sciences, Kyushu University)
SESSION P1 - Applications (1)
Data Processing of Synthetic Aperture Radar (SAR) on the Cellular Array
Processor (CAP)
Makoto Ono, Shigeki Kuzuoka, Yoshimitsu Tanaka (Mitsubishi Electric
Corporation Kamakura Works)
Takashi Kan, Hiroyuki Miyata, Tetsuaki Isonishi (Mitsubishi
Electric Corporation Information Systems and Electronics
Development Laboratory)
A Parallel Image Recognition System and Its Application to Quality
Judgement by Image Analysis
Kazuyoshi Inoue, Takashi Koezuka, Hidenobu Arita (Electronics R&D Lab,
Nippon Steel Co.)
The Implementation of Parallel Processing for Molecular Evolutionary Analysis
Using a Highly Parallel Processor
Kimitoshi Naito, Masahito Kawai, Atsuko Kishino (FACOM-HITAC
Limited)
Etsuko N. Moriyama, Kazuho Ikeo, Yasuo Ina, Takashi Gojobori
(National Institute of Genetics)
Morio Ikesaka, Hiroyuki Sato (Fujitsu Laboratories, Limited)
SESSION P2 - Applications (2)
Performance Evaluation of the Superscalar Processor "Shimpu" based on SIMP
(Single Instruction System/Multiple Instruction Pipelining) Architecture
Morihiro Kuga, Kazuaki Murakami, Shinji Tomita (Interdisciplinary
Graduate School of Engineering Sciences, Kyushu University)
Naohiko Irie (Current affiliation: Hitachi Ltd.)
QCD Simulation with Parallel Computer QCDPAX
Yoshio Oyanagi (Institute of Information Sciences, University of
Tsukuba)
Yoichi Iwasaki, Kazuyuki Kanaya, Tomoteru Yoshie (Institute of
Physics, University of Tsukuba)
Tsutomu Hoshino, Tomonori Shirakawa (Institute of Engineering
Mechanics, University of Tsukuba)
Shingo Ichii (KEK, National Laboratory for High Energy Physics)
Toshio Kawai (Department of Physics, Keio University)
Cenju: A Multiprocessor System for Modular Circuit Simulation
Toshiyuki Nakata, Norio Tanabe, Nobuki Kajihara, Satoshi Matsushita,
Hiromi Onozuka (NEC Corporation)
Yoshihiro Asano, Nobuhiko Koike (NEC Scientific Information System
Development Ltd.)
SESSION P3 - Applications (3)
The Demand-Driven Replay System for Parallel Programs based on Shared
Objects: Implementation and Evaluation
Naohisa Takahashi (NTT Software Laboratories)
Evaluation of Inter-processor Communication in the KL1 Implementation on
the Multi-PSI
Katsuto Nakajima (Mitsubishi Electric Corporation)
Yu Inamura, Nobuyuki Ichiyoshi (ICOT)
Evaluation of Parallel Execution of the ATMS with a Parallel Lisp
Hiroshi G. Okuno (NTT Software Laboratories)
SESSION P4 - Neural Networks
A RISC Processor Array for ANN
Atsunobu Hiraiwa, Shigeru Kurosu, Shigeru Arisawa, Makoto Inoue
(Sony Corporate Research Laboratories)
Neural Divide-and-Conquer Method and its Application for LSI Module Placement
Problem
Shigeru Oyanagi (Research & Development Center, Toshiba
Corporation Kawasaki-shi, 210, Japan)
An Application of the Preprocessing System LS-M on the Parallel Machine
(SM)2 II - A Learning Algorithm based on Neural Network
X.P. Ling, H. Amano, Y. Anzai (Faculty of Science and
Technology, Keio University, Japan)
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