rick@cs.arizona.edu (Rick Schlichting) (11/06/90)
[Dr. David Kahaner is a numerical analyst visiting Japan for two-years
under the auspices of the Office of Naval Research-Far East (ONRFE).
The following is the professional opinion of David Kahaner and in no
way has the blessing of the US Government or any agency of it. All
information is dated and of limited life time. This disclaimer should
be noted on ANY attribution.]
[Copies of previous reports written by Kahaner can be obtained from
host cs.arizona.edu using anonymous FTP.]
To: Distribution
From: David Kahaner ONRFE [kahaner@xroads.cc.u-tokyo.ac.jp]
H.T. Kung CMU [ht.kung@cs.cmu.edu]
Re: Aspects of Parallel Computing Research in Japan--Summary.
Date: 6 Nov 1990
ABSTRACT. Some aspects of parallel computing research in Japan are
analyzed, based on authors' visits to a number of Japanese universities
and industrial laboratories in October 1990. This portion of the report
contains a summary and recommendations.
INTRODUCTION.
During the two week period 1-10 October 1990, the authors attended the
InfoJapan '90 meeting in Tokyo, the 1990 Japan Electronics Show, also in
Tokyo, and visited a number of Japanese universities and industrial
laboratories, including Kyushu University, Tsukuba University,
Electrotechnical Laboratory, NEC, Hitachi, Fujitsu, Sanyo, and
Matsushita research Labs. Kung also had brief visits to IBM Tokyo
Research Laboratory, Intel Japan and the Institute of Statistical
Mathematics. The goal of this visit to Japan was to study and assess
Japanese research activities in computing generally and parallel
processing in particular. Kung had been to Japan several times, but not
since 1986. He knew several of the researchers we visited, as some of
them had previously spent time at CMU. Kahaner had been to some of the
same labs and reported on these in earlier articles. Building on these
contacts we have been able to construct the summary and assessment
report below. Such a report can neither be complete nor static; research
projects change targets, mature, and their relevance changes with
respect to other work. Because of the time limitation, we were not able
to visit all the projects we wanted to see. Our comments, conclusions,
and recommendations are based only on those projects familiar to both of
us. Others will be reported on later and may force us to alter some of
the conclusions below.
The report is divided into four parts.
PART 1. The current part is an overall summary and assessment, with
conclusions and recommendations. Some of these are based on evaluations
of specific research, others on intuition and experience. A few of our
comments are controversial, and sometimes the authors disagreed with
each other on the conclusions, but we decided to only issue one report
in order to facilitate reading.
The remaining parts contain background information about the specific
projects that we saw and in some cases background about the
organizations that we feel help to put their research in better
perspective.
PART 2. Contains descriptions of supercomputing and parallel computing
activities at NEC and Fujitsu. It also contains some new benchmark
figures for supercomputers from these companies. A general outline of
all the remaining parts is also given at the beginning of PART 2.
PART 3. Deals with parallel computing at Hitachi and Matsushita, and
some observations about the Japan Electronics Show 1990.
PART 4. Deals with parallel computing at Kyushu and Tsukuba
Universities, Electrotechnical Laboratory, Sanyo Electric, and the New
Information Technology project.
The following outline describes the topics that are discussed in the
various parts of this report.
PART 1 (this part) OUTLINE-----------------------------------------------
INTRODUCTION
SUMMARY
RECOMMENDATIONS
PART 2 OUTLINE----------------------------------------------------------
FUJITSU OVERVIEW
Company profile and computer R&D activities
VP2000 series supercomputer organization and performance
PARALLEL PROCESSING ACTIVITIES
SP (Logic Simulation Engine)
AP1000 (Cellular Array Processor)
RP (Routing Processor)
ATM (Asynchronous Transfer Mode) Switch
MISCELLANEOUS FUJITSU ACTIVITIES
Neurocomputing
HMET
NEC
SX-3 series supercomputer organization and performance
Benchmark data for SX-3, VP2000, and Cray.
Comments
MISCELLANEOUS NEC PARALLEL PROCESSING ACTIVITIES
PART 3 OUTLINE----------------------------------------------------------
HITACHI CENTRAL RESEARCH LABORATORY
HDTV
PARALLEL AND VECTOR PROCESSING
Hyper crossbar parallel processor, H2P
Parallel Inference Machine, PIM/C
Josephson-Junctions
Molecular Dynamics
JAPAN ELECTRONICS SHOW, 1990
HDTV
Flat Panel Displays
MATSUSHITA ELECTRIC
Company profile and computer R&D activities
ADENA Parallel Processor
MISCELLANEOUS ACTIVITIES
HDTV
Comments about Japanese industry
PART 4 OUTLINE---------------------------------------------------------
KYUSHU UNIVERSITY
Profile of Information Science Department
Reconfigurable Parallel Processor
Superscalar Processor
FIFO Vector Processor
Comments
ELECTROTECHNICAL LABORATORY
Sigma-1 Dataflow Computer and EM-4
Dataflow Comments
CODA Multiprocessor
NEW INFORMATION PROCESSING TECHNOLOGY
Summary
Comments
UNIVERSITY OF TSUKUBA
PAX
SANYO ELECTRIC
Company profile and computer R&D activities
HDTV
END OF OUTLINE-------------------------------------------------------
SUMMARY.
In Japan, parallel processing is being seriously considered by both
industry and universities, but Japan is still two or three years behind
the U.S. in this area. (Parallel machines here refer to distributed
memory parallel machines.) The Japanese possess outstanding hardware and
packaging capabilities, and definitely have advantages in hardware.
They are experimenting with a substantial number of standard as well as
innovative parallel architectures and interconnection networks; some
have been under development and evolution for ten years or more. Most
of Japanese parallel machines at present are special purpose rather than
general purpose. How quickly can they catch up? The real problems in
parallel processing are software, computation models and application
related issues, and, we feel that the U.S. will probably keep the lead
for the foreseeable future. However, using outstanding hardware strength
to remove some major bottlenecks in parallel processing is a real
possibility which cannot be ignored.
Japanese industry's interest in parallel machines at present is probably
mostly for image building (and spin-off technologies) and for internal
use (to meet some special computation demands such as logic simulation
of large hardware designs) rather than for possible profit from
commercial sales. This is similar to their initial reasons for entering
the supercomputer business several years ago. Strictly speaking, at
this time there are no general purpose parallel machines commercially
available from any Japanese company. Several have been "announced",
such as PAX (DSV6450) from Anritsu or AP1000 from Fujitsu, but we are
not aware of any deliveries.
Parallel processing research at Japanese national labs and universities
in general pursues niche areas related to some specific applications or
computation models. Examples include Tsukuba's PAX (for quantum
chromodynamics simulation), Kyoto's ADENA (for partial differential
equations computation), and ETL's dataflow machines. The projects are
mostly small and generally isolated from each other. Most of the
projects design new hardware which is then fabricated by an industrial
partner. The projects show ample determination and some of them exhibit
a high-degree of creativity, but a main difficulty seems to be the
meager budgets and small staff in most university departments. However,
the Japanese Government seems to have recently recognized that
university projects need better support and the current budget proposals
attempt to address this specific issue.
In the area of supercomputers, Japanese single processor supercomputers
are at least as fast as those in the U.S., based mostly on their chip
and packaging expertise. They follow diligently software and
applications development efforts in the U.S. and do the work mostly by
themselves. In the hardware area, they excel in all aspects of
supercomputers ranging from 20,000 gate high-speed (70 picosecond) logic
chips, to high-density multi-chip packages and to peripherals such as
high transfer rate (19.6 MBytes/sec) disk arrays. There is no single
area that a company will give up. Several Japanese companies have these
broad base infrastructures.
The Japanese industry has some special advantages in technology
transfer. Most of the researchers in industrial labs we saw were young
and only a small percentage have Ph.D degrees; older, more senior
research staff are often moved over to development, production or
management, and thus help guide corporate policy. We saw little evidence
of senior researchers giving "pure" research directions, and most of the
research directions appear to be from the development side with research
projects jointly defined between the research and development groups.
Companies seem very well informed about research, particularly in the
west, and they appear to be wise about the relation of profit to
research. They show real persistence in key emerging technology, but do
not appear to go crazy about anything.
In general we were very impressed with pervasiveness of the technology,
persistence in key technology, stability of research support, awareness
of research and maturity in positioning the role of research, and the
success of technology transfer and product engineering laboratories. In
the area of VLSI, Japanese are well known for their manufacturing
capability. However, their capability in ASIC (Application Specific
Integrated Circuits) is at least equally impressive. These capabilities
will be of great importance in future high performance systems.
On the other hand the collaboration between university researchers in
Japan or between them and their industrial counterparts is not as strong
as in the U.S. There are some joint research/development projects
between companies and universities, but these are not common. Perhaps
the large amount of research done in industry discourages
inter-organization collaboration. Computer networks available to the
research community are modest by U.S. standards. Very few percentages
of homes have computer access and the fastest wide area networks are
mostly at 48KBits/second or 64Kbits/second. This is a significant
weakness in Japanese scientific communication and one that the
government is trying to turn around.
The persistence of research has some downside too. We have seen some
anecdotal evidence of a lack of flexibility in research directions. One
example is related to dataflow computers. We have also seen this
phenomena in the Prolog hangup associated with the 5-th generation
project and wonder if the same might not occur in fuzzy logic in due
time. Western researchers seem to have less difficulty changing
directions. Our problem is actually that we sometimes move too fast to
a new direction without fully exploiting or understanding an older one.
On the other hand we know many Japanese researchers who are very much
willing to reorient their work when science, fashion, or budgets change.
Research environments in Japan and U.S. are quite different. As noted
above, the industrial researchers we met were all young. Kung observed
that "I don't think that I know of any serious systems researchers in
Japanese industrial labs who are over 35 years old." There seem to be
very few career paths in Japanese industry to accommodate senior
researchers. Name cards often list people as Researcher, Senior
Researcher, Chief Research, Senior Chief Researcher, but most often the
more senior people have substantial responsibilities in development,
management, or administration. On the other hand we know many very
senior staff in U.S national labs who, much like some university
professors, have only their own research to be responsible for. (We
wonder if this is one reason Americans are strong in research, whereas
Japanese are good in making product?) Finally, both Kahaner and Kung
noticed the (typically Japanese) crowded office space for researchers.
A researcher will literally have no more table space left if he or she
has one workstation monitor and one PC. This must have given them all
the motivation to work on flat panel displays to save space. We wonder
if anyone has studied the effect of community workspace versus private
workspace with respect to research productivity?
RECOMMENDATIONS.
This is a good time for U.S. parallel machine vendors to sell products
to Japan. Marketing needs to aggressively explain the advantages of
using the best products as tools for further research rather than
reinventing everything. Creative marketing must also recognize and adapt
to the financial constraints that are imposed on Japanese university
researchers.
Research support for parallel computing has been strong in the U.S. The
current lead that U.S. enjoys in parallel processing is a direct result
of the foresight of the industry and federal funding agencies; U.S.
started to support serious research efforts in this area literally many
years before Japan. To keep the lead, continued support is essential.
More urgently, however, is the translation of the lead into a new,
sustaining capability of using parallel processing for real-world
applications. Our experiences in Japan suggest a few points that we
wish to emphasize.
It is important to encourage research in parallel processing software
and applications, and in packaging technology specifically and
manufacturing in general. This represents later activities in a product
development cycle, beyond the initial design of new computation models
and parallel architectures. We feel that the success the Japanese have
had in developing profitable advanced technology is partly due to their
emphasis on the last steps in the entire process of involving a new idea
or technology into a product. It is the quality of the "last
10-percent" effort that decides who ultimately benefits from the
technology by being able to offer a competitive product. However, this
"last 10-percent" effort demands paying attention to incremental
improvements, quite different from the traditional academic research
goal which encourages conceptual, paradigm shift. This calls for
expanding the goal of academic research and the corresponding
adjustments in research funding policies.
Parallel processing becomes most significant when the machine can scale
up to have a large number of processors. We need to encourage research
directly addressing software and hardware issues related to very large
scale parallel machines. An example is research in fault-tolerance of
large scale parallel machines, an area essential to the eventual,
practical use of these machines. In Japan and U.S., large parallel
systems for QCD simulations already use hundreds of boards; the
reliability of these systems have been a major concern. We probably can
handle 1,000 board systems, but to make teraflops machines we will
likely need 10,000 boards based on technology available in the
foreseeable future. There is no way we will be able to keep a teraflops
machine running unless fault tolerance is designed in from the
beginning.
An urgent agenda for the U.S. industry and scientific communities is to
substantially improve their awareness of Japanese research and
development activities. U.S. gets a great deal of information on
technical developments in Japan, but does less well in making it
available to people who really need the information, whether for
research or policy. In the high-performance computing area, U.S.
researchers and developers still have very limited knowledge of what is
happening in Japan, especially in Japanese industry, although the
situation is improving. Technical reporting (such as this, we hope) is
very helpful, but it must reach the people who are actually doing or
directing the technical work. Scientific liaison activities such as NSF
and DoD are important, and should be active and involved, sponsoring
conferences, etc. We recommend that the liason activities be expanded
significantly to allow routine participation from the U.S. industry and
scientific communities.
---------------END OF PART 1----------------------------------------