phil@amd70.UUCP (Phil Ngai) (05/17/84)
A week ago I said I had a circuit I thought was an edge-triggered D type
flip flop implemented in a combinational PAL. Here it is:
D ----- -----
--------| | ------- |-------| | ------- Q
| |AND|---| S Q |----| |AND|---| S Q |----
| --o| | | | ---| | | |
| | ----- | | | ----- | |
| | ----- | | | ----- | |
----o| | | | |-------| | | |
| |AND|---| R Q/|----| | |AND|---| R Q/|
--o| | ------- ---| | -------
CLK | ----- | -----
--------------------------------
The basic idea is that the first RS FF gets set by the low phase of the
clock and this is passed to the second RS FF in the high phase of the clock.
During the low phase, the second FF will not change in response to changes
in the first FF. During the high phase the second FF could change but
the first FF can not change. Q can therefore only change when the clock
changes from low to high.
This is also a master-slave type of flip flop, although that term seems to
commonly be used to describe a FF which changes when the clock changes
from high to low. Note that there are race conditions possible if D
changes while the clock is going from 0 to 1. 7474s have setup and hold
times and so does this circuit. 7474s also have race conditions if you
violate their setup and hold times. This circuit is slower than a 7474 and
a metastable state could persist longer, thus this circuit is probably not
suitable as an arbiter. I leave it to the reader to determine what uses it
can be put to.
In case anyone doesn't know yet, you can implement an RS FF with one output
of a PAL as follows:
Q = SET + /RESET * Q
I also suggest looking at Hill and Peterson, "introduction to SWITCHING
THEORY AND LOGICAL DESIGN", 2nd edition, page 429, for further treatment
of this topic.
Hope the readers have found this article enlightening. Use more PALs.
--
Phil Ngai (408) 749-5286 {ucbvax,decwrl,ihnp4,allegra,intelca}!amd70!phil