mccalpin@MASIG1.OCEAN.FSU.EDU ("John D. McCalpin") (03/23/89)
Does anyone know what kind of cache miss delays are incurred on the various machines in the 4D line? I am specifically interested in the Personal IRIS and the 4D/60. On the LINPACK numbers that I posted earlier, the difference is clearly associated with the fact that a Personal IRIS has an 8 kB data cache and the 4D/60 has (at least) a 32 kB data cache. The equivalent MIPS machine (M-800) has a 64 kB data cache. The LINPACK code requires something not too far over 40 kB of data space, and the hit rate would be much better on the 4D/60. In order to estimate performance on my big codes, I can assume LOTS of cache misses, so the performance will be largely determined by how much latency is incurred on a data cache miss --- especially since SGI is not currently shipping the MIPS cache re-ordering part of the optimizer.... One more necessary item in the formula is how big a memory chunk is loaded on a cache miss. I think that this is called the cache line size. Does anyone know this value for the machines? I would guess it to be the same for all R-2000-based machines, but you can never tell.... -- ---------------------- John D. McCalpin ------------------------- Mesoscale Air-Sea Interaction Group & Department of Oceanography & Supercomputer Computations Research Institute - Fl State Univ. mccalpin@masig1.ocean.fsu.edu mccalpin@nu.cs.fsu.edu mccalpin@fsu (BITNET or MFENET) SCRI::MCCALPIN (SPAN) ------------------------------------------------------------------
len@synthesis.Synthesis.COM (Len Lattanzi) (03/23/89)
One clarification on the Mips compiler cache-reorganizer. This only
reorders procedures to fit better in the icache.
-Len
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