gnu@sun.uucp (John Gilmore) (08/14/84)
Yes, the 68000 (and 68008, 68010, and 68020) can all rerun a parity error fetch. If you assert Bus Error and Halt simultaneously, the CPU will halt, and when they are removed, it will rerun the bus cycle that was in process. This is great for recovering from transient parity errors in hardware, and for other things too. In the 68010 and 68020 it is even possible to stop in mid-instruction, poke around looking at the problem, possibly refresh the page from disk, or whatever, and then resume the instruction at the failing memory cycle. You can also supply data to replace the failing memory cycle and the CPU will go on with the instruction as if that fetch had returned that data. The catch is that the Bus Error signal has to appear before the data is valid (and not TOO long after the Data Transfer Acknowledge signal has been asserted); this means that if you want to do reruns or bus errors on parity errors, you must run slower than top speed (or use more expensive memory chips). This is why Suns just report parity errors in the next cycle rather than trying to retry in the current cycle. Note that ECC requires that the CPU wait not only for the data to be valid, but also for the code to be checked and then possibly for the data to be corrected.