malpass@LL-VLSI.ARPA (Don Malpass) (12/28/87)
Would you believe that, at this late date, I've uncovered an error on Heath's H-207 card that I'd not heard about before? It will ONLY hurt you if you use 8" drives that want more precompensation delay than the 120 uS specified for the 5" drives. My MFE drive (JRV take note) is one such, although it seems to have been happy for the last 5 years with 120 uSec. The error is in the board etch; not the schematic. If you blindly carry out the card-mod procedure in the book and illustrated by the two Insets of Pictorial 18, you will be puzzled by what looks like an error in Inset #2; but the real error is that U11-1 goes to J2-A on the board, rather than J2-B, as the schematic correctly shows. Since A and B are tied together on an unmodified board, most users are unaffected. But if you want to increase the 8" compensation delay, you're supposed to cut the etch between them and add a jumper between B and C. Due to the PC layout error, nothing then works, (because B now isn't connected to anything) and until you also cut the etch from U11-1 to J2-A and add a wire from U11-1 to J2-B (where the schematic says it belongs) you're in trouble. Now that I've done that, I've been able to adjust the two precomp pots properly, and my 8" disks should now become more reliable. Gern: maybe a less wordy version of this belongs in the Z-100 hardware mod archives. I assume there's no point in telling Heath about the error - I've yet to hear word-one from them about bugs I know they've been told about. don [malpass@LL-vlsi.arpa]