sauer@ibmchs.UUCP (Charlie Sauer) (04/19/88)
The current RT Advanced Processor Card includes a 20 MHz 68881 as a floating
point co-processor. There is an optional "Advanced Floating Point Accelerator"
(AFPA) card which uses an ADSP 3221 ALU, 3210 multiplier and 1401 sequencer.
The microcode on the AFPA provides trigonometric and other functions. There is
a gate array that goes between either of these and the ROMP-C fixed point
processor. The gate array presents a 68020-like interface to the 68881 and
presents a DMA-like interface to the ROMP, so that fixed point and floating
point operations can proceed concurrently. I don't know of any externally
available documentation on these other than the Hardware Technical Reference,
SV21-8024. (Orderable at IBM branch offices.)
The original RT processor card has no built in floating point processor.
An FPA for the original processor card is described in Scott M. Smith,
"Floating Point Accelerator" in RT Personal Computer Technology SA23-1057,
January 1986. That FPA uses an NS32081.
AIX provides a DMA-like floating point compatibility interface which is bound
to the process at exec time so that object code can be compiled to be
independent of the floating point hardware. This interface has sufficiently
low overhead that AIX does not provide a direct interface to the 68881. A
direct interface to the AFPA is provided. The compatibility interface is
documented in AIX Operating System Technical Reference Version 2.1, SBOF-0135.
All of the above are designed to be compliant with IEEE P754 10.1.
--
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