brunner@bullhead.uucp (08/17/90)
Subject: Patch to test AFPA for IBM RT 6150 with IBM/4.3
Index: /usr/src/ibm/{afpacode.c,dma_sync.s,Makefile}
Description:
The Advanced Floating Point Accelerator (AFPA) is an adapter
that works with the IBM RT 6150. The AFPA adapter is loaded
with microcode on booting by the utility "afpacode".
This package includes code to test the AFPA more comprehensively.
It tests almost every AFPA instruction when booting-up, and
whenever the afpacode command is executed. It does not
alter behavior for other floating point hardware like FPA
68881, or software emulation.
This code causes some 93 AFPA instructions tests to be run.
The normal output should look something like:
The AFPA is already online.
afpacode: begin afpa_test
afpacode: afpa tests correct=93, failures=0
If you get failures, you should call your IBM Service Engineer.
The package is a shar file which contains 2 files:
V1.34.patch - a patch to afpacode.c and the Makefile
dma_sync.s - an assemble routine called to sync the FP registers
Fix: You need to be super-user to apply this patch.
1. Save a copy of this file.
2. Follow the instructions below to unshar this file.
3. "cd /usr/src/ibm" (cd to afpacode source directory)
4. "patch < V1.34.patch" (apply the patch)
5. "make afpacode" (make new version of afpacode)
6. "afpacode" (running afpacode should show 93 correct tests)
6. "make install" (install the new afpacode)
Eric Brunner, Consultant, IBM AWD Palo Alto (415) 855-4486
inet: brunner@monet.berkeley.edu uucp: uunet!ibmsupt!brunner
# This is a shell archive. Save it in a file, remove anything before
# this line, and then unpack it by entering "sh file". Note, it may
# create directories; files and directories will be owned by you and
# have default permissions.
#
# This archive contains:
#
# V1.34.patch
# dma_sync.s
#
echo x - V1.34.patch
sed 's/^X//' >V1.34.patch << 'END-of-V1.34.patch'
X*** Makefile Mon Aug 6 15:54:18 1990
X--- Makefile.fix Thu Aug 27 22:29:23 1970
X***************
X*** 12,23 ****
X #
X SHSCRIPT=support mergesym
X #
X! STD= afpacode cvtsym omerge makesym pf kbdlock untty ftc whichfpa
X NONSTD= dosread
X DOSLINKS=dosdir doswrite dosdel
X DIR=/usr/ibm
X
X! all: ${STD} ${NONSTD} ${SUBDIR}
X
X clean:
X rm -f ${STD} ${NONSTD} ${DOSLINKS} *.o
X--- 12,23 ----
X #
X SHSCRIPT=support mergesym
X #
X! STD= cvtsym omerge makesym pf kbdlock untty ftc whichfpa
X NONSTD= dosread
X DOSLINKS=dosdir doswrite dosdel
X DIR=/usr/ibm
X
X! all: afpacode ${STD} ${NONSTD} ${SUBDIR}
X
X clean:
X rm -f ${STD} ${NONSTD} ${DOSLINKS} *.o
X***************
X*** 27,33 ****
X ${STD}:
X ${CC} -o $@ $?
X
X! afpacode: afpacode.o
X
X cvtsym: cvtsym.o
X omerge: omerge.o
X--- 27,34 ----
X ${STD}:
X ${CC} -o $@ $?
X
X! afpacode: afpacode.o dma_sync.o
X! ${CC} -o $@ afpacode.o dma_sync.o
X
X cvtsym: cvtsym.o
X omerge: omerge.o
X***************
X*** 48,53 ****
X--- 49,55 ----
X
X install: all ${DESTDIR}/${DIR}
X install -c -m 444 keyboard_codes ${DESTDIR}/usr/lib/keyboard_codes
X+ install ${IFLAGS} afpacode ${DESTDIR}/${DIR}/afpacode
X for i in ${STD} ${NONSTD} ; do \
X install ${IFLAGS} $$i ${DESTDIR}/${DIR}/$$i; done
X for i in ${DOSLINKS}; do \
X*** afpacode.c Wed Jul 18 09:54:04 1990
X--- afpacode.c.fix Thu Aug 27 22:29:53 1970
X***************
X*** 1465,1470 ****
X--- 1465,2338 ----
X }
X }
X
X+ #define DELAY(x) fpa_delay(x)
X+ int
X+ fpa_delay(x)
X+ int x;
X+ {
X+ while (--x >= 0);
X+ return(x);
X+ }
X+
X+ #define afpa_read_status() *(int volatile *) (FPA_BASE | 0x00dfb8)
X+ #define afpa_read_status_comp() ((afpa_read_status() >> 10) & 0x3)
X+ #define afpa_write_status(stuff) *(int volatile *) (FPA_BASE | 0x043fb8) = stuff
X+
X+ /*
X+ * More comprehensive testing of AFPA
X+ * One test for each testable op code.
X+ */
X+
X+ #define DN1 0xbff00000
X+ #define D_1 0x3ff00000
X+ #define D_11 0x3ff19999
X+ #define D_11L 0x9999999a
X+ #define D_2 0x40000000
X+ #define D_3 0x40080000
X+ #define D_4 0x40100000
X+ #define FN1 0xbf800000
X+ #define F_1 0x3f800000
X+ #define F_125 0x3fa00000
X+ #define F_2 0x40000000
X+ #define F_3 0x40400000
X+ #define F_9 0x41100000
X+
X+ int
X+ afpa_test()
X+ {
X+ int bad = 0;
X+ int good = 0;
X+ int i;
X+
X+ static double d_1 = 1;
X+ static double dn1 = -1;
X+ static double d_2 = 2;
X+ static double d_4 = 4;
X+ double d; /* double referenced thru long pointer */
X+ long int *dp = (long int *)&d;
X+
X+ int volatile dma_test[] = {0x0, 0x1, 0x2, 0x3};
X+ int volatile dma_input[4];
X+
X+ fprintf(stderr,"afpacode: begin afpa_test\n");
X+
X+ /* ABSS r0=-1; r2=|r0|=1 */
X+ afpa_write_register(0,FN1);
X+ *(int volatile *) (FPA_BASE | 0x01d408) = 0;
X+ DELAY(10);
X+ i = afpa_read_register(2);
X+ if (i == F_1) ++good; else ++bad;
X+
X+ /* ABSIS r2=|r0(=-1)|=1 */
X+ *(int volatile *) (FPA_BASE | 0x09d408) = FN1;
X+ DELAY(10);
X+ i = afpa_read_register(2);
X+ if (i == F_1) ++good; else ++bad;
X+
X+ /* ABSL r0r1=-1; |r0r1|=r2r3=1 */
X+ d = 0;
X+ afpa_write_register(0,DN1);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x01d008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* ABSIL r1=-1L; |r0(=-1H)r1|=r2r3=1 */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x09d008) = DN1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* ADDS r2=1; r3=1; r2+r3=2 */
X+ afpa_write_register(0,F_1);
X+ afpa_write_register(2,F_1);
X+ *(int volatile *) (FPA_BASE | 0x010408) = 0;
X+ DELAY(10);
X+ i = afpa_read_register(2);
X+ if (i == F_2) ++good; else ++bad;
X+
X+ /* ADDIS r3=1; r2(=1)+r3=2 */
X+ afpa_write_register(3,F_1);
X+ *(int volatile *) (FPA_BASE | 0x09048c) = F_1;
X+ DELAY(10);
X+ i = afpa_read_register(3);
X+ if (i == F_2) ++good; else ++bad;
X+
X+ /* ADDSI r2=1; r3(=1)+r2=2 */
X+ afpa_write_register(2,F_1);
X+ *(int volatile *) (FPA_BASE | 0x05048c) = F_1;
X+ DELAY(10);
X+ i = afpa_read_register(3);
X+ if (i == F_2) ++good; else ++bad;
X+
X+ /* ADDL r0r1=1; r2r3=1; r0r1+r2r3=2 */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_1);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x010008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* ADDIL r1=1L; r2r3=1; r0(=1H)r1+r2r3=2 */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_1);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x090008) = D_1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* ADDLI r0r1=1; r3=1L; r0r1+r2(=1H)r3=2 */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x050008) = D_1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* COMS r2=1; r3=1; (r2==r3)=0 */
X+ afpa_write_register(2,F_1);
X+ afpa_write_register(3,F_1);
X+ *(int volatile *) (FPA_BASE | 0x01248c) = 0;
X+ DELAY(10);
X+ if (afpa_read_status_comp() == 0) ++good; else ++bad;
X+
X+ /* COMIS r3=1; (r2(=1)==r3)=0 */
X+ afpa_write_register(3,F_1);
X+ *(int volatile *) (FPA_BASE | 0x09248c) = F_1;
X+ DELAY(10);
X+ if (afpa_read_status_comp() == 0) ++good; else ++bad;
X+
X+ /* COML r0r1=1; r2r3=1; (r0r1==r2r3)=2 */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_1);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x012008) = 0;
X+ DELAY(10);
X+ if (afpa_read_status_comp() == 0) ++good; else ++bad;
X+
X+ /* COMIL r1=1L; r2r3=1; (r0(=1H)r1==r2r3)=0 */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_1);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x092008) = D_1;
X+ DELAY(10);
X+ if (afpa_read_status_comp() == 0) ++good; else ++bad;
X+
X+ /* CSL */
X+ d = 0;
X+ afpa_write_register(0,F_1);
X+ *(int volatile *) (FPA_BASE | 0x006c08) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* CISL */
X+ d = 0;
X+ *(int volatile *) (FPA_BASE | 0x086c08) = F_1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* CLS */
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x005808) = F_1;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* CILS */
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x005808) = D_1;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* CWS */
X+ afpa_write_register(0,0x1);
X+ *(int volatile *) (FPA_BASE | 0x001c08) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* CIWS */
X+ *(int volatile *) (FPA_BASE | 0x001c08) = 0x1;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* CWL */
X+ d = 0;
X+ afpa_write_register(0,0x1);
X+ *(int volatile *) (FPA_BASE | 0x000c08) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* CIWL */
X+ d = 0;
X+ *(int volatile *) (FPA_BASE | 0x080c08) = 0x1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* COPS */
X+ afpa_write_register(0,F_1);
X+ afpa_write_register(2,0xf);
X+ *(int volatile *) (FPA_BASE | 0x011408) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* COPL */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,0xf);
X+ afpa_write_register(3,0xf);
X+ *(int volatile *) (FPA_BASE | 0x011008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* DIVS */
X+ afpa_write_register(0,F_1);
X+ afpa_write_register(2,F_2);
X+ *(int volatile *) (FPA_BASE | 0x018408) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_2) ++good; else ++bad;
X+
X+ /* DIVIS */
X+ afpa_write_register(2,F_2);
X+ *(int volatile *) (FPA_BASE | 0x098408) = F_1;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_2) ++good; else ++bad;
X+
X+ /* DIVSI */
X+ afpa_write_register(0,F_1);
X+ *(int volatile *) (FPA_BASE | 0x058408) = F_2;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_2) ++good; else ++bad;
X+
X+ /* DIVL */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_2);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x018008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* DIVIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_2);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x098008) = D_1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* DIVLI */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x058008) = D_2;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* FSW */
X+ afpa_write_register(0,F_125);
X+ *(int volatile *) (FPA_BASE | 0x00fc08) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* FISW */
X+ *(int volatile *) (FPA_BASE | 0x08fc08) = F_125;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* FLW */
X+ afpa_write_register(0,0x3ff19999);
X+ afpa_write_register(1,0x9999999a);
X+ *(int volatile *) (FPA_BASE | 0x00ec08) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* FILW */
X+ afpa_write_register(1,0x9999999a);
X+ *(int volatile *) (FPA_BASE | 0x08ec08) = 0x3ff19999;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* LOCKFP - tested in init */
X+
X+ /* MULS */
X+ afpa_write_register(0,F_1);
X+ afpa_write_register(2,F_2);
X+ *(int volatile *) (FPA_BASE | 0x01c408) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_2) ++good; else ++bad;
X+
X+ /* MULIS */
X+ afpa_write_register(2,F_2);
X+ *(int volatile *) (FPA_BASE | 0x09c408) = F_1;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_2) ++good; else ++bad;
X+
X+ /* MULSI */
X+ afpa_write_register(0,F_1);
X+ *(int volatile *) (FPA_BASE | 0x05c408) = F_2;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_2) ++good; else ++bad;
X+
X+ /* MULL */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_2);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x01c008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* MULIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_2);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x09c008) = D_1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* MULLI */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x05c008) = D_2;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* NEGS */
X+ afpa_write_register(0,FN1);
X+ *(int volatile *) (FPA_BASE | 0x015408) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* NEGIS */
X+ *(int volatile *) (FPA_BASE | 0x015408) = FN1;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* NEGL */
X+ d = 0;
X+ afpa_write_register(0,DN1);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x015008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* NEGIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x095008) = DN1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* RDFR - tested many times */
X+
X+ /* RDER - untestable */
X+
X+ /* RDSTR - tested above */
X+
X+ /* RDSCX - tested in init */
X+
X+ /* RSW */
X+ afpa_write_register(0,F_125);
X+ *(int volatile *) (FPA_BASE | 0x009c08) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* RISW */
X+ *(int volatile *) (FPA_BASE | 0x089c08) = F_125;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* RLW */
X+ afpa_write_register(0,D_11);
X+ afpa_write_register(1,D_11L);
X+ *(int volatile *) (FPA_BASE | 0x008c08) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* RILW */
X+ afpa_write_register(1,D_11L);
X+ *(int volatile *) (FPA_BASE | 0x088c08) = D_11;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* SUBS */
X+ afpa_write_register(0,F_1);
X+ afpa_write_register(2,F_2);
X+ *(int volatile *) (FPA_BASE | 0x014408) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* SUBIS */
X+ afpa_write_register(2,F_2);
X+ *(int volatile *) (FPA_BASE | 0x094408) = F_1;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* SUBSI */
X+ afpa_write_register(0,F_1);
X+ *(int volatile *) (FPA_BASE | 0x054408) = F_2;
X+ DELAY(10);
X+ if (afpa_read_register(2) == F_1) ++good; else ++bad;
X+
X+ /* SUBL */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_2);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x014008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* SUBIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_2);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x094008) = D_1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* SUBLI */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x054008) = D_2;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* TSKSWU - tested in init */
X+
X+ /* TSW */
X+ afpa_write_register(0,F_125);
X+ *(int volatile *) (FPA_BASE | 0x00bc08) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* TISW */
X+ *(int volatile *) (FPA_BASE | 0x00bc08) = F_125;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* TLW */
X+ afpa_write_register(0,D_11);
X+ afpa_write_register(1,D_11L);
X+ *(int volatile *) (FPA_BASE | 0x00ac08) = 0;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* TILW */
X+ afpa_write_register(1,D_11L);
X+ *(int volatile *) (FPA_BASE | 0x00ac08) = D_11;
X+ DELAY(10);
X+ if (afpa_read_register(2) == 0x1) ++good; else ++bad;
X+
X+ /* WTFR - tested many times */
X+
X+ /* WTSTR - tested in init */
X+
X+ /* DISCS - tested in init */
X+
X+ /* RCS - tested in init */
X+
X+ /* RDIR */
X+ i = *(int volatile *) (FPA_BASE | 0x02fc00);
X+ *(int volatile *) (FPA_BASE | 0x02ec00) = 0x55555555;
X+ i = *(int volatile *) (FPA_BASE | 0x02fc00);
X+ if (i == 0x55555555) ++good; else ++bad;
X+
X+
X+ /* TSKSWD - untestable */
X+
X+ /* WCS - tested in init */
X+
X+ /* ATANL */
X+ d = 0;
X+ afpa_write_register(0,0x0);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x035008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* ATANIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x0b5008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* ATAN2L */
X+ d = 0;
X+ afpa_write_register(0,0x0);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x014808) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* ATAN2IL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x094808) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* COMTS, COMTIS - ? */
X+
X+ /* COMTL, COMTIL - ? */
X+
X+ /* COSL */
X+ d = 0;
X+ afpa_write_register(0,0x0);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x030808) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* COSIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x0b0808) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* EXPL */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x036008) = 0;
X+ DELAY(10);
X+ if ((afpa_read_register(2))==0x4005bf0a & (afpa_read_register(3))==0x8b145769)
X+ ++good; else ++bad;
X+
X+ /* EXPIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x0b6008) = D_1;
X+ DELAY(10);
X+ if ((afpa_read_register(2))==0x4005bf0a & (afpa_read_register(3))==0x8b145769)
X+ ++good; else ++bad;
X+
X+ /* INTL */
X+ d = 0;
X+ afpa_write_register(0,D_11);
X+ afpa_write_register(1,D_11L);
X+ *(int volatile *) (FPA_BASE | 0x032808) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* INTIL */
X+ d = 0;
X+ afpa_write_register(1,D_11L);
X+ *(int volatile *) (FPA_BASE | 0x0b2808) = D_1;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* LOGBL */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x015808) = 0;
X+ DELAY(10);
X+ dma_sync();
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* LOGBIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x095808) = D_1;
X+ DELAY(10);
X+ dma_sync();
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* LOG10L */
X+ d = 0;
X+ afpa_write_register(0,D_1);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x037808) = 0;
X+ DELAY(10);
X+ dma_sync();
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* LOG10IL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x0b7808) = D_1;
X+ DELAY(10);
X+ dma_sync();
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* LOGL */
X+ d = 0;
X+ afpa_write_register(0,0x4005bf0a);
X+ afpa_write_register(1,0x8b145769);
X+ *(int volatile *) (FPA_BASE | 0x037008) = 0;
X+ DELAY(10);
X+ dma_sync();
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* LOGIL */
X+ d = 0;
X+ afpa_write_register(1,0x8b145769);
X+ *(int volatile *) (FPA_BASE | 0x0b7008) = 0x4005bf0a;
X+ DELAY(10);
X+ dma_sync();
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* MODL */
X+ d = 0;
X+ afpa_write_register(0,D_2);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_3);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x010808) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* MODIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_3);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x090808) = D_2;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* NOOP */
X+ *(int volatile *) (FPA_BASE | 0x027c00) = 0;
X+ ++good;
X+
X+ /* REML */
X+ d = 0;
X+ afpa_write_register(0,D_2);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_3);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x018808) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == dn1) ++good; else ++bad;
X+
X+ /* SCALBL */
X+ d = 0;
X+ afpa_write_register(0,0x0);
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_1);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x01c808) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* SCALBIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ afpa_write_register(2,D_1);
X+ afpa_write_register(3,0x0);
X+ *(int volatile *) (FPA_BASE | 0x09c808) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_1) ++good; else ++bad;
X+
X+ /* SINL */
X+ d = 0;
X+ afpa_write_register(0,0x0);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x030008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* SINIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x0b0008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* SQRS */
X+ afpa_write_register(0,F_9);
X+ *(int volatile *) (FPA_BASE | 0x019408) = 0;
X+ DELAY(10000);
X+ dma_sync();
X+ if (afpa_read_register(2) == F_3) ++good; else ++bad;
X+
X+ /* SQRIS */
X+ *(int volatile *) (FPA_BASE | 0x099408) = F_9;
X+ DELAY(10000);
X+ dma_sync();
X+ if (afpa_read_register(2) == F_3) ++good; else ++bad;
X+
X+ /* SQRL */
X+ d = 0;
X+ afpa_write_register(0,D_4);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x019008) = 0;
X+ DELAY(10);
X+ dma_sync();
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* SQRIL */
X+ d = 0;
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x099008) = D_4;
X+ DELAY(10);
X+ dma_sync();
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == d_2) ++good; else ++bad;
X+
X+ /* TANL */
X+ d = 9999;
X+ afpa_write_register(0,0x0);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x031008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* TANL */
X+ d = 9999;
X+ afpa_write_register(0,0x0);
X+ afpa_write_register(1,0x0);
X+ *(int volatile *) (FPA_BASE | 0x0b1008) = 0;
X+ DELAY(10);
X+ *dp = afpa_read_register(2);
X+ *(dp+1) = afpa_read_register(3);
X+ if (d == 0) ++good; else ++bad;
X+
X+ /* WTIR */
X+ i = *(int volatile *) (FPA_BASE | 0x02fc00);
X+ *(int volatile *) (FPA_BASE | 0x02ec00) = 0x55555555;
X+ DELAY(10);
X+ i = *(int volatile *) (FPA_BASE | 0x02fc00);
X+ DELAY(10);
X+ if (i == 0x55555555) ++good; else ++bad;
X+
X+ /* DO NOT SEPERATE BELOW */
X+
X+ /* DMA Write Register Sequential Instruction */
X+ *(int volatile *) (FPA_DMA_BASE | 0x1e7c03) = 0x4;
X+ *(int volatile *) (FPA_DMA_BASE | 0x067c0b) = (int) &dma_test;
X+ DELAY(10);
X+ dma_sync();
X+ if ((afpa_read_register(2) == 0x0) & (afpa_read_register(3) == 0x1)) ++good; else ++bad;
X+
X+ /* DMA Read Register Sequential Instruction */
X+ dma_input[0]=0x55555555;
X+ dma_input[1]=0x55555555;
X+ *(int volatile *) (FPA_DMA_BASE | 0x3e7c83) = (int) &dma_input;
X+ DELAY(10);
X+ dma_sync();
X+ if ((dma_input[0] == 0x0) & (dma_input[1] == 0x1)) ++good; else ++bad;
X+
X+ /* WRLN */
X+ if ((dma_input[0] == 0x0) & (dma_input[1] == 0x1)) ++good; else ++bad;
X+
X+ fprintf(stderr,"afpacode: afpa tests correct=%d, failures=%d\n",good,bad);
X+ return(bad);
X+ }
X+
X+
X void
X usage(argv0)
X char *argv0;
X***************
X*** 1672,1678 ****
X if (rc == 0) {
X fprintf(stderr, "The AFPA is already online.\n");
X }
X! exit(0);
X }
X if ((state.hardware_state&FLOAT_AFPA_CONTROL_STORE_ENABLE) == 0) {
X fprintf(stderr, "The kernel did not enable access to AFPA ucode;");
X--- 2540,2546 ----
X if (rc == 0) {
X fprintf(stderr, "The AFPA is already online.\n");
X }
X! exit(afpa_test()); /* Test online AFPA */
X }
X if ((state.hardware_state&FLOAT_AFPA_CONTROL_STORE_ENABLE) == 0) {
X fprintf(stderr, "The kernel did not enable access to AFPA ucode;");
X***************
X*** 1834,1839 ****
X--- 2702,2708 ----
X } else {
X printf("Adapter type is AFPA.\n");
X }
X+ return(afpa_test()); /* Test operational AFPA */
X }
X return 0;
X }
END-of-V1.34.patch
echo x - dma_sync.s
sed 's/^X//' >dma_sync.s << 'END-of-dma_sync.s'
X .globl .oVncs
X .set .oVncs,0
X .globl _dma_sync
X .globl _.dma_sync
X .data
X .align 2
X_dma_sync:
X .long _.dma_sync
X .text
X_.dma_sync:
X clrsb r15,8 # DMA sync
X br r15
X
END-of-dma_sync.s
exit
Eric Brunner, Consultant, IBM AWD Palo Alto (415) 855-4486
inet: brunner@monet.berkeley.edu uucp: uunet!ibmsupt!brunner
trying to understand multiprocessing is like having bees live inside your head.