ptw@encore.UUCP (P. Tucker Withington) (02/09/85)
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NCR (I think) announced a 32-bit microprogrammable chip set a while back, and I
haven't heard anything about it since. Does anyone use it? Whatever happened
to it?
Or was I dreaming?
o.o --tucker
~wescott@ncrcae.UUCP (Mike Wescott) (02/11/85)
The NCR 32 bit chip set is used by NCR in a few of our larger machines, such as the 9300. Honeywell has signed some kind of licensing agreement so that they can use the chip set. Some general info follows, but be forewarned that my information is skimpy and not necessarily up to date. Perhaps some of NCR's people from the West Coast plants will comment and correct me where I'm wrong. The NCR/32 CPU and MMU are supposed to be available in 8Mz versions. The CPU is known as the "CPC" (Central Processing Chip????) and the MMU is called the Address Translation Chip (ATC). The other support chips are a serial I/O controller (SIC), an math chip (EAC) - whatever that means - (its an FPU of some kind), and a VAC - Virtual Assist Chip, that offloads the CPC in a virtual address environment. The CPC contains 16 general 32-bit registers and is microprogrammed externally. More info should be available from your local sales office. But you'll probably have to push it. Another development of possible interest is the GAPP chip. It's a an array of 72 processors on a single chip. GAPP is reportedly 10x faster than the system it replaces, with a 8 to 1 size reduction. The chip was designed for Martin Marietta and will be used by them in military applications of image processing. NCR retains marketing rights for commercial and industrial applications. Mike Wescott NCR Corp. mcnc!ncsu!ncrcae!wescott akgua!usceast!ncrcae!wescott
bobbyo@celerity.UUCP (Bob Ollerton) (02/13/85)
We are using the NCR 32000 CPC as the foundation for the CPU in
the Celerity C1200 workstation. We run it at 125ns, direct execution
(no microcode, I.E. compilers emit the CPC's native instruction set) with
over 4000 stack cache registers, so it ended up being "RISC-like".
The CPU has 4 I/O busses, three of them 32-bit, the fourth one
is for instructions (from cache) and is 16bits wide (CPC design).
We added a seperate but integrated floating point and extended
math (trig, sqrt, etc...) IEEE co-processor as we did not like
the NCR offerings. About 80% of the instructions execute in one
CPC cycle or about 8 mips. We get a conservative 2Million single
precision, and 1.5Million double precision, Whetstones per sec.
The 32000 has been run faster... The January 18th Argonne labs
LINPACK benchmark results contain the C1200 execution times,
which were quite good.
NCR 32000 was designed to have external microcode which would
allow it to emulate other CPUs, such as IBM 370... NCR uses it
in their 9300 series products. There are some features of the NCR 32000
that we did not use. We choose to use it in direct execution versus
emulation mode inorder to take advantage of its raw speed.
NCR announced a Multibus based CPU board using the 32000 this past
fall. Seems to be targeted for designers, who would use it to
build a prototype.
We are very happy with the way the NCR 32000 worked out for us, the
product speaks for its self. Being 5 miles south of NCR, and having
certain former NCR employees at Celerity may have had an effect on our
success!
If there is a negative side, I would guess it to be complexity
of design necessary to use the chip set. Its not like plunking
in a 68010 with some ram to produce yet another 90 day 68K
wonder.
I don't have anything specific on how we implemented the 32000 at
this time, I do have some general product information on the
C1200 workstation. If you would like a copy, drop me a note.
Please note that I work for Celerity in Product Marketing
(well, I am "Product Marketing"!).
Best Regards,
Bob.
--
Bob Ollerton; Celerity Computing;
9692 Via Excelencia; San Diego, Ca 92126; (619) 271 9940
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