mlh@houxl.UUCP (M.HARRISON) (05/01/85)
<EAT THIS LINE>
By now some of you may have read that we (AT&T) are for the
first time selling commercially our WE32100 32 bit
microprocessor family (now aka "The UNIX Microsystem",
thanks to someone in marketing). I'm not going to comment
on the performance of our chipset relative to the other 32
bit vendors out there (Motorola and National), as I'm sure
this information will be forthcoming from less biased
sources. Suffice to say that we think its pretty good.
However, I'd like to give some details on the devices.
All members of the chipset have full 32 bit address and data
buses and are implemented in 1.5 micron CMOS. The
cornerstone chips are the WE32100 CPU and WE32101 MMU. The
devices were initially developed for in-house use over the
last few years. They've been through several iterations and
are now mature and more importantly bug-free (as far as we
know!) Also available is an 80 bit (double extended
precision) IEEE standard floating-point Math Accelerator
Unit. Single-precision arithmetic is also supported. This
guy really flies, 80 bit register to register multiplies
take 67 cycles and adds take 23. It operates as a tightly-
coupled co-processor with our CPU or as a peripheral to
other 32 bit processors. Also announced, but not available
till third quarter this year are DRAM and DMA Controllers.
All devices come in two speeds, 10 and 14 MHz.
One neat feature is our packaging, they are rectangular
ceramic pin grid arrays. Pins are on 100 mil centers with
every third row missing to allow for a routing channel on
the PC board. This will generally reduce the number of
layers in the PC board and allow more effective power and
ground routing, thereby enhancing low-noise operation. On
the top of each package is an array of small rectangular
metal pads, each on corresponding to the pin below it. We
call them scratch pads, they're great for scope probing.
ZIF and LIF sockets are available.
As far as prototyping goes, there is an evaluation board
that facilitates hardware and software experimentation
(including varying wait-states!). For development, we're
offering a Hardware-Software Development System which
provides in-circuit emulation, a high-level debugger which
resides partly in firmware and partly on a UNIX host, and a
plug-in interface to the HP 64000 Logic Development System.
For software, there is a C compiler, an assembler, and many
other packages available. Basically, if it runs on a 3B-2,
it can be made to work on the chipset.
If there's interest, I'll be happy to either post or e-mail
more info. If you want data sheets feel free to call
(800) 372-2447.
Marc Harrison
AT&T Bell Labs, Holmdel
(201) 949-1779doug@terak.UUCP (Doug Pardee) (05/03/85)
I must be getting ever more cynical in my old age. I read the WE32100
info posted here, and my immediate reaction was that it must not be
a very impressive CPU.
This impression was brought about because they're touting the
fabrication technology (1.5 micron CMOS) and packaging (ceramic pin grid
arrays on 100 mil centers with gaps for routing channels), but haven't
said "boo" about the internal architecture, instruction set, and speed
(except for the FPU's speed).
Does it have registers? How long does a memory cycle take? What kind
of addressing modes are available? Does it have any on-chip cache? How
much time penalty does branching incur? Does it have separate I/O
addressing a la Intel, or is I/O memory mapped? Can instructions
operate on 8, 16, and 32-bit data? Do the operands have to be aligned
in memory? Can it do a 32-bit multiply and divide? Does it have string
handling instructions? Does it have bit field instructions?
Was I supposed to have fallen to my knees and bowed my face to the
ground because this 32-bit processor announcement came from AT&T?
--
Doug Pardee -- Terak Corp. -- !{ihnp4,seismo,decvax}!noao!terak!doug