dennisg@sdcrdcf.UUCP (Dennis E. Griesser) (08/19/85)
I am tossing together a micro with a Z-80 and lots of memory (at least 64K).
The natural choice is DRAMs. There will be eight sockets and the design should
be able to accept 64K or 256K parts.
The problem is refresh.
To keep parts low, the Z-80's built-in refresh timing will be used. Sadly, the
Z-80's internal refresh counter is only 7 bits wide. This will take care of
some of the 64K chips on the market, but not all of them. All of the 256K DRAM
specs that I have seen require 8 bits of refresh (luckily not 9).
My alternatives seem to be as follows:
o commercial DRAM controller
o self-refreshing RAMs
o refresh in software (execute 256 NOPs)
o external tri-state 8-bit counter (74xx590)
o find Z-80 with 8-bit refresh
The commercial DRAM controllers seem like overkill. I would like to avoid
self-refreshing RAMs. Software refresh seems risky and would require periodic
interrupts to tell the CPU when to refresh. That leaves me two questions:
o Is the 74xx590 a real part? I have seen specs from various vendors, but
a friend claims that they are impossible to find!
o Do later versions or second-sources of the Z-80 have a wider refresh
counter?
Thank you, in advance!
[standard disclaimers apply]michaelk@azure.UUCP (Mike Kersenbrock) (08/23/85)
> I am tossing together a micro with a Z-80 and lots of memory (at least 64K). > The natural choice is DRAMs. There will be eight sockets and the design should > be able to accept 64K or 256K parts. > > The problem is refresh. > > To keep parts low, the Z-80's built-in refresh timing will be used. Sadly, the > Z-80's internal refresh counter is only 7 bits wide. This will take care of > some of the 64K chips on the market, but not all of them. All of the 256K DRAM > specs that I have seen require 8 bits of refresh (luckily not 9). 1.- Use one of the CMOS Z80s, like the NSC800 which if memory serves me right, has the 8th bit. 2.- Add JUST the 8th bit. If parts count is a problem, you could "do it" with a single PAL package.
BillW@SU-SCORE.ARPA (William Chops Westfield) (08/24/85)
Although 256K and some 64K memorys require 256 refresh cycles, they do
not require them as often as rams requiring only 128 cycles. On top
of that, the z80 does many more refresh cycles than are actually
required (one after EVERY opcode fetch, I think). Therefore, It is
a relatively simple matter to add an extra flip flop or two outside
of the z80. (well, perhaps not THAT simple, but:)
My 1982 TI Memory data book has an applications brief to do exactly this
on page 211 entitled "256-cycle refresh conversion". Hmm, I think I
can even reproduce it:
_____
A7 >-----------------------------------------+ 1 |
/--------------\ | OUT+-----> address A7 to mplx
| | /--------+0 SEL|
| 74ls393 | / \__+__/ 1 of 2 data selector
\ _______+________+_ | (eg 74ls157, leftover
\ / A B C D A B C D | | mplx unit, etc.)
Z80 \ | 1 2 | |
signals \ | CLKA CLKB | |
|\ \ \____+________+____/ |
74ls04 | \ \ | | |
/--+ O-(-----/ from |
| | / \------------ Q1D |
| |/ |
RFSH>----+--------------------------------------/
Enjoy
BillW