hull@hao.UUCP (Howard Hull) (08/25/85)
> > Some knowledgable comment would be appreciated. (A small flame here - please > do not post a response to a request for information if you only *think* you > know the answer (as many did to the original request), this only confuses > the issue - flame off). > > Ray Dunn ..philabs!micomvax!othervax Knowledgeable comment seems to be a scarce commodity on the net, Ray, so I usually try to submit some data with my speculations. I think it's completely unfair to restrict articles from the net just because people don't know what they are talking about. If you placed such restrictions on politicians, we could not likely even form a government! One simple way of looking at the UV-EPROM charge loss characteristic is merely to set up a series of resistor/capacitor circuits with a distribution of resistance values. The equation for the discharge is given by E=Vo*(1-exp(-t/RC)) in each case. A family of such curves shows the traditional exponential decay with all curves crossing any arbitrary threshold with various slopes, dependent on the mean and standard deviation values of the resistance, R. A resultant bit loss versus time characteristic would likely appear as depicted below: % of cells OK 100 ------\ \ \ \ 0 \--------- 0 20 Time, years This function has a portion whose linearity and width depends on the distribution of the resistance values and the relative threshold. The way the tests are carried out, the IC manufacturers do not look at the parts until the tests are over, so they don't know where the transition occurred. They do, however, use tests of different lengths. The tests show the following, for 2732A EPROMS: # of 10 * bad 9 parts 8 per 7 2000 6 parts 5 under 4 * test at 3 125 deg 2 * C non- 1 * cumulative 0 168 500 1000 2000 Hours The elevated 125 degree C temperature accelerates the failure rate (according to the Arrhenius Plot) by a factor of from 10 to 20000, depending on the failure mechanism. The test results show little logical correlation with the curve I depicted above for a set of RC models, unless the points have high statistical variance. For that case, the data fit a beginning loss time of around a few hundred hours. It does not seem possible to assign an "all units finally failed" time to this data except by extrapolation. There is no basis here for the linearity of the extrapolation function. Moreover, the sample size for the 168 hour test was ~2200 parts, the 500 hour test used ~1000 parts, the 1000 hour test used ~1000 parts, and the 2000 hour test used ~200 parts and the failures were down in the quantum levels. Under the circumstances, I would hesitate to comment on the linearity of the loss of bits, but I will note that one can draw a line in any of several ways through the above group of points, and use that as an assumed linear failure rate to predict an estimate of rate of failure; I assure you that this is commonly done, truthful or not. The people who do the testing assure all of us that they can predict reliability from this data. They even publish papers discussing the various techniques they use. AND NOW, since it's Saturday (too bad if you get this on Wednesday) for those of you who are not yet sound asleep, the following should do the trick, the Data: 2732A Reliability Engineering Evaluation Report Bruce Euzent, Ron Vitt Reliability Engineering, INTEL Corp. SUMMARY Qualification testing of INTEL's high performance HMOS-E 32K EPROM has established HMOS as a reliable process (Note 1) for the fabrication of UV eraseable EPROMs. High temperature dynamic liftesting was used to evaluate the long term failure rate. At 55 degrees C and a 60% UCL (user confidence level), a failure rate of .032%/1000 hours was observed based on 1.3 million device hours of 125 degree C lifetesting. RELIABILITY TESTING AND RESULTS Five categories of testing were used to assure the electrical reliability of the 2732A: 1. High Temperature Dynamic Lifetest 2. High Temperature Reverse Bias (HTRB) 3. High Temperature Storage 4. Temperature Cycling 5. Low Temperature Lifetest High Temperature Dynamic Lifetest -- This test is used to accelerate failure mechanisms by operating the devices at an elevated temperature of 125 degrees C. During the test the memory is sequentially addressed and the outputs are exercised, but not monitored or loaded. A checker- board data pattern is used to simulate random patterns expected during actual use. Results of lifetesting on the 2732A are shown in Table 1 along with the failure analysis. In order to best determine long term failure rate all devices used for lifetesting are subjected to standard INTEL screening. The 48 hour burn-in results measure infant mortality and are not included in the failure rate calculation. Failure rate calculations are shown in Table 2 for each relevant activa- tion energy. Failure rate calculations are made using the appropriate energy (see Notes 1,2,3) and the Arrhenius Plot as shown in Figure 1 (*). The total equivalent device hours at a given temperature can be determined. The failure rate is then calculated by dividing the numbers of failures by the equivalent device hours using a chi-square distribution to arrive at a confidence level associated failure rate. A conservation [sic] estimate of the failure rate is obtained by including the zero based failure rate for 0.3eV failures. A failure rate of 0.032%/1000 hours at 55 degrees C and 0.064%/1000 hours at 70 degrees C using 60% UCL are determined for the 2732A. Devices for the other stresses received a 168 hour lifetest prior to stressing. *The activation energies for various failure mechanisms are listed in Table 3. Table 1. Lifetset Results Burn-in | 125 Degree C Dynamic | 150 Degree C HTRB | 48HR | 168HR | 500HR | 1K HR | 2K HR | 168HR | 500HR | 1K HR | 0/293 | 0/293 | 0/112 | 0/112 | 0/86 | 0/50 | 0/50 | 0/50 | 0/306 | 0/306 | 2/138E| 0/136 | -- | 0/47 | 0/47 | -- | 0/94 | 0/94 | 0/32 | 0/32 | 0/32 | -- | -- | -- | 1/80 A | 0/79 | 0/42 | 0/42 | 0/42 | -- | -- | -- | 1/102B | 0/101 | 0/41 | 0/41 | 1/41 K| -- | -- | -- | 0/355 | 0/355 | 0/100 | 0/100 | -- | 0/98 | 0/98 | -- | 1/486C | 1/485D| 0/88 | 0/88 | -- | -- | -- | -- | 0/191 | 0/191 | 0/191 | 1/191F| -- | -- | -- | -- | 1/426J | 0/21 | 0/21 | -- | 1/21G | 0/20 | 0/20 | 0/20 | 0/336 | 0/336 | 0/252 | 0/252 | -- | 1/83H | 1/82I | 0/81 | Totals: 4/2669 |1/2261 |2/1017 |1/1015 | 1/201 | 2/299 | 1/297 | 0/151 | A=Part array unprogrammed G=Multi edge bit charge retention, contamination B=Single bit charge retention H=Input leakage, contamination C=Single bit charge retention I=Input leakage, contamination D=Single bit charge retention (0.6eV) J=Single bit charge retention E=2 each single bit charge retention (0.6eV) K=Single bit charge retention (0.6eV) F=Single bit charge retention (0.6eV) High Temperature Reverse Bias (HTRB)--This test is performed at 150 degrees C and is effective for testing for leakage failures, device parameter drift, and data retention. HTRB results are included in the lifetest summary but are not used for the failure rate calculation. Three failures were observed in 299 units tested due to contamination. High Temperature Storage--Another common test is high temperature storage in which devices are subjected to 250 degrees C with no applied bias. This test is used to detect mechanical reliability problems (e.g. bond integrity), process stability, and data retention. Results from this test are shown in Table 4. Thirteen failures were observed from 532 devices tested due to single bit charge loss or contamination. Temperature Cycle--This test consists of cycling the temperature of the chamber housing the devices from -65 degrees C to +150 degrees C. This test is used to detect mechanical reliability problems and microcracks. Results are shown in Table 4. No rejects were found on 81 devices. Low Temperature Lifetest--This test is performed to detect the effects of hot electron injection into the gate oxide (Note 2) as well as package related failures (corrosion of the internal metal lines, etc.). This test is performed at -10 degrees C with Vcc = 5.0 volts. Results are shown in Table 4. One reject in 100 devices was found for single bit charge retention. Table 2. Failure Rate Predictions Actual Device | Equivalent Device Hours |Failure Rate/1000 Hours(60%UCL)| Hours @ 125 C | Ea | 55 C | 70C | #Fail | 55 C | 70 C | 1.32X10^6 | 0.6eV | 3.6X10^7 | 1.5X10^7 | 5 | 0.017% | 0.041% | 1.32X10^6 | 0.3eV | 6.9X10^6 | 4.5X10^6 | 0 | 0.015% | 0.023% | Combined Failure Rate | 0.032% | 0.064% | Fits*| 320. | 640. | *FIT = Failures in time, 1 FIT=1 Failure per 10^6 Device Hours. Table 3. Failure Mechanism Activation Energies Relevant to EPROMs | Failure Mode | Activation Energy | |Random bit charge gain/loss | 0.6eV | |Oxide breakdown | 0.3eV | |Silicon Defects | 0.3eV | |Contamination | 1.0-1.4eV | Table 4. Stress Results | 250 Degree C Bake | -10 Degree C Dynamic | Temperature | | 48HR | 168HR | 500HR | 500HR | 1K HR | | Cycle | | 0/50 | 0/50 | 0/50 | 0/25 | 0/25 | | 0/20 | | 1/48A | 0/47 | 1/47E | 1/25H | 0/24 | | 0/20 | | 0/50 | 0/50 | 1/50F | -- | -- | | -- | | 0/25 | 0/25 | 0/25 | -- | -- | | -- | | 1/49B | 0/48 | 2/48G | -- | -- | | -- | | 1/49C | 0/48 | 0/48 | 0/25 | 0/25 | | 0/20 | | 0/99 | -- | -- | 0/25 | -- | | -- | | 3/75D | 0/72 | 0/72 | -- | -- | | 0/21 | | 2/87I | 0/85 | 1/85J | -- | -- | | -- | Totals: | 8/532 | 0/425 | 5/425 | 1/100 | 0/74 | | 0/81 | A,B,C,D,H=Single bit charge retention E,F,G=Multi edge bit charge retention, contamination I=1ea. single bit charge retention 1ea. input leakage, contamination J=Input leakage, contamination Notes: 1. S. Rosenberg, D. Crook, B. Euzent, "16th Annual Proceedings of the International Reliability Physics Symposium," pp 19-25, 1978. 2. J. Caywood, B. Euzent, B. Shiner, "Data Retention in EPROMS," 1980 IEEE International Reliability Physics Symposium. 3. S. Rosenberg, B. Euzent, "HMOS Reliability" Reliability Report RR-18, INTEL Corporation, 1979. [Omitted: Figure 1. Arrhenius Plot on log-log paper 1 cycle reversed in the abscissa, labeled "TEMPERATURE", range 250 at left, 25 at right; 7 cycles in the ordinate, labeled "ACCELERATION FACTOR", range 10^0 at bottom to 10^6 for top cycle floor. Four linear lines plotted to converge at the lower left, with various positive slopes symmetric around the plot diagonal, upward and to the right, labeled from top to bottom 1.4eV, 1.0eV, 0.6eV, and 0.3eV. 1.4eV leaves the graph at x=100 y=4X10^6 1.0eV leaves the graph at x=39 y=4X10^6 0.6eV leaves the graph at x=25 y=4X10^4 0.3eV leaves the graph at x=25 y=1.5X10^2 Very messy to reproduce on USENET. Bit Map description paragraph and Figure 2., depicting the test bit map. ] Howard Hull {ucbvax!hplabs | allegra!nbires | harpo!seismo } !hao!hull
ray@othervax.UUCP (Raymond D. Dunn) (08/27/85)
Organization: >> Some knowledgable comment would be appreciated. (A small flame here - please >> do not post a response to a request for information if you only *think* you >> know the answer (as many did to the original request), this only confuses >> the issue - flame off). >> >> Ray Dunn ..philabs!micomvax!othervax >Knowledgeable comment seems to be a scarce commodity on the net, Ray, so I >usually try to submit some data with my speculations. I think it's completely >unfair to restrict articles from the net just because people don't know what >they are talking about. If you placed such restrictions on politicians, we >could not likely even form a government! > > Howard Hull In general yes, however when people ask for specific technical info, then they are not asking for opinions, they are asking for facts. All that opinions create is traffic from people contradicting those opinions by other opinions which creates traffic from..... Ray Dunn. ..!philabs!micomvax!othervax!ray