skeller@xenna.Encore.COM (Shaun Keller) (02/15/90)
Errata for the book "Series 32000 Programmer's Reference Manual" by Colin Hunter copyright 1987. Shaun Keller 7 February 1990 These are things I noted while writing a 32k disassembler. I've divided my comments into several categories. It would be nice if these came with the book, perhaps as stickers for inside the front cover. Just Plain Wrong 1. Page 6-202. Binary format shows ADDi where SUBi should be. 2. Page 6-61. Bit 15 in CMPST should be a 1 not a 0. 3. Page A-5. Under Register/Stack Manipulation missing entry for BISPSRB and BISPSRW. 4. Page 5-7. Table 5-1. Access class regaddr only uses general purpose registers not FPU registers. Remove the "Fn". 5. Page 6-135. Operand access class and length "write.i" should be moved from "quick" to "gen". Formatting Errors 1. Page 6-141. Move the dest and gen to line up with write.W for MOVXBW. 2. Page 5-5. Remove the underscore from "access_classes" second paragraph line 3. 3. Page A-4. The entire second line beginning with "Supervisor Call" should not be in bold face. 4. Page 6-106. Operand list for INSSi "offset, length" spacing should look the same as that for EXTSi on page 6-90. 5. Page 6-63. Example for CMPSB is incorrectly formatted. "0E" should be moved right to group with "04 00" Suggestions for Improved Presentation 1. Several instructions contain short fields for what are really special purpose opcode or operand bits. It is more useful to replace these shorts with new special purpose field names. The same is true for implied operands that are immediates. I suggest the following names. cond in Bcond Scondi CMFI in SETCFG mmureg in LMR SMR procreg in LPRi SPRi save-regs in ENTER SAVE restore-regs in EXIT RESTORE offset-length-byte in EXTSi INSSi 2. Page 5-26 (maybe elsewhere). Reg fields only specify general purpose registers not FPU regs. 3. Page 5-20. Put the comment "Displacements are tagged with length bits." under the description of absolute mode. 4. Page 2-34. Say that gen immediates can only have lengths B, W, D, F, or L because all other possible encodings exclude the immediate address mode (e.g., 2i is always access class rmw). 5. Should update everything to show the differences between the 032, 332, and 532. This is especially needed for those instructions that access special registers like LMR, SMR, and LPRi and SPRi. 6. If for Bcond and Scondi you can use 14 and 15 in the cond field for unconditionally true (shadowed by BR) and unconditionally false, then add UT and UF to the cond tables for these instructions.