aglew@dwarfs.crhc.uiuc.edu (Andy Glew) (08/31/90)
[Please respond by email - I read this newsgroup, but it has a very
short expiration time at my site]
Can anyone help me understand the Encore's sbitib and tbitib
interlocked instructions?
I am particularly interested in understanding their behaviour on the
Multimax I'm working on at UIUC CRHC, which is an 8 processor '532
based machine, I believe. (I cannot find the equivalent of uname -a
to make sure).
My understanding is that sbitib is actually the '532's exchange with
memory operation - Encore's hardware recognizes this, and instead of
doing an RMW on the bus, sends a special bus transaction that causes
the memory card to write a 1 to the location, and returns the old
value. Encore fakes out the RMW to the processor.
How far off is this?
How does sbitib interact with the cache? Does it bypass the cache?
Does it short circuit, return the old value without a bus transaction
if the old value in the cache is a 1? Does it make the value exclusive
in the local cache? If the value is already exclusive in the local
cache, does sbitib not require any bus transactions?
My understanding was that sbitib always went to the bus, but maybe
I'm wrong.
What happens if multiple sbitib initiated bus transactions for the
same location are initiated? Do they all go to the bus one after
another, or do they somehow get combined?
My understanding is that they all go to the bus.
How many bus transactions does the following code produce?
0 (if already in cache), 1, or 6?
sbitib $0, 0(4(sp)) /* # Set bit atomically */
sbitib $0, 0(4(sp)) /* # Set bit atomically */
sbitib $0, 0(4(sp)) /* # Set bit atomically */
sbitib $0, 0(4(sp)) /* # Set bit atomically */
sbitib $0, 0(4(sp)) /* # Set bit atomically */
sbitib $0, 0(4(sp)) /* # Set bit atomically */
Any help in this would be appreciated.
--
Andy Glew, a-glew@uiuc.edu [get ph nameserver from uxc.cso.uiuc.edu:net/qi]