JOHANSSON@ICDC.LLNL.GOV (Erik) (01/08/88)
In answer to Peter Knopf's question regarding a Transputer board with a Q-Bus interface: We have a board that we designed ourselves which interfaces a Micro VAX to a network of 64 Transputers. To spare the time involved in designing the Q-Bus interface circuitry and writing the associated I/O driver, we used a DEC DRV11-WA general purpose Q-Bus DMA interface board (the DRV11 has a relatively simple interface, and uses XADRIVER, which comes with VMS). All we needed to do was design a network I/O board to interface between the DRV11 and the network of processors. We use two 4Kx16 bit FIFOs to buffer the data flow between the DRV11 and an I/O Transputer on the board. A command interpreter and state machine controls the interface between the DRV11 and the FIFOs. On the Transputer side of the FIFOs there is a word recombination circuit, controlled by a state machine, which combines two 16 bit words into a 32 bit word (or vice versa, depending on the direction of the transfer) and places the result in a register mapped into the Transputer's memory space. The Transputer can poll the status flags on the FIFOs during transfers, or use some special circuitry which activates the Event Request line when the FIFOs require attention. The interface to the network of 64 processors is achieved through the four links on the Transputer. The I/O board is implemented on a double Eurocard wire-wrap board (we are in the process of converting it to a PC board). All the logic on the board is implemented in three XC2064 programmable logic chips manafactured by Xilinx. The links on the I/O transputer are buffered using 74LS240s, impedance matching resistors, and twisted pair wire. The 4Kx16 FIFOs are each implemented using two 4Kx9 FIFOs manafactured by IDT. The DRV11 is capable of transferring 250 KW/S (500 KB/S) in single cycle mode, and 500 KW/S (1 MB/S) in burst mode. It does not currently support block mode transfers on the Q-Bus. We are able to use both single cycle and burst mode transfers with our I/O board. In addition, we have been evaluating some third party Q-Bus boards which claim to be DRV11-WA compatible AND support block mode transfers; however, we have not found any which work and follow the DRV11-WA interface specification properly. Our I/O board has been up and running for about a year (although it has been improved upon several times). We are now capable of transfering large images (512x512x32) from the Micro VAX to the network for image processing, and back to the VAX for display, quickly enough to do interactive image processing. Erik M. Johansson, M/S L-54 Anthony J. De Groot, M/S L-156 Lawrence Livermore National Laboratory P.O. Box 808 Livermore, CA 94550