ADRIAN@vax.oxford.ac.UK (08/23/88)
Data Acquisition Hardware
=========================
Our data acquisition board is now at the prototype stage. It is a T212/T222
system which has special peripherals attached, particularly a fancy A/D
conversion circuit. It has special features to support SIMD arrays. (Our
project integrates SIMD arrays with transputers.)
The simplest application is as part of a transputer system passing data
on the links. The SIMD features need not be used.
If anyone would like any prototype boards *at your own risk*, please
contact me very soon. The risk in the UK should be less than {pounds sterling}
200, excluding VAT. (A British tax.)
If there is sufficient demand, we may arrange a 'production' run: if you
are seriously interested, please let me know.
Appended is a more detailed provisional description.
Adrian Lawrence
Microprocessor Unit,
Oxford University,
13,Banbury Road,
Oxford, Oxon.
OX2 6NN.
UK.
ADRIAN @ UK.AC.OXFORD.VAX
EARN/Bitnet: ADRIAN%UK.AC.OXFORD.VAX@AC.UK
{EARN node UKACRL}
ARPA: ADRIAN%VAX.OXFORD.AC.UK
ACSnet: adrian@vax.oxford.ac.uk@au.oz.munnari
[ean.ac.uk%nummari.cs.mu]
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ACQSYS DESCRIPTION
ACQSYS is primarily a data acquisition system. It is a single
circuit board which is NETBUS compatible. It also supports the
standard up/down interface used on 'B00 boards'. A flash analogue to
digital converter delivers data to a 64K block of fast static RAM.
The normal sampling rates are from 1 to 16 Msamples/sec, selected by
software using an internal clock. The sampling clock may also be
supplied externally, perhaps for sychronisation with a video source.
There is no lower bound to the sampling rate.
The analogue input has a bandwidth of at least 100MHz. No anti-
aliasing filter is provided. This is because there is a peak hold
mode available: when selected, the peak value of the input signal
during each sample period is digitized.
ACQSYS includes a T2 transputer, T212 or T222, with 8KB of fast
RAM giving a total of 10 or 12KB transputer memory. A 20MHz
transputer will run at full speed without wait states. Apart from the
event pin, this subsystem may be used independently: ACQSYS is a
significant computational resource even when it is not busy with
analogue data.
The digitized analogue data can be passed out of ACQSYS in a number of
ways.
1. There is a conventional parallel port.
2. The data is available to the transputer and so may be passed on
the transputer links, although it will often be at least partially
processed on board.
3. ACQSYS can 'corner-turn' on the fly.
ACQSYS was initially designed as a component of a larger system,
integrating SIMD (Single Instruction Multiple Data) architecture with
transputers (Multiple Instruction Multiple Data), while supporting a
much wider range of applications. 'Corner-turning' is the conversion
between ordinary parallel words and the serial streams used by most
SIMD systems.
The board may be used with conventional computers: the minimum
requirement is a link adapter card. ACQSYS is initialized by loading
a program down a link. Thereafter it can perform computations and
control data acquisition as required, perhaps passing processed
results or raw data across the link. The raw data may also be read
via the parallel port.
Also provided is a digital to analogue converter and a 4 bit
output port. There are further status and control signals available.
These facilities might be used to control a stepper motor, for
example, perhaps in connection with data acquisition.
Extensive use of programmable logic devices allows ACQSYS to be
customized: it may be possible to produce variants for special
applications.
DETAILS
The first part of the memory map is occupied by RAM: internal
and 8KB external. The system is controlled through PORTS normally
mapped at addresses starting at 6000 hexadecimal. A configuration
port sets the sample clock frequency, the source of the analogue
output, and the manner in which the analogue input is handled.
Further ports set and read the frame registers which specify the
destination of the digitised data and how many samples are required.
When 'corner-turning' is active, the precision is written to a
further port (see below). Other output ports control the
initialization of data acquisition in the case when the transputer
exercises that function; the 4 bit general purpose output; the
digital to analogue converter, and the pulse output. During active
data acquisition, a signal ACQUIRE is asserted. This signal is
available both to the transputer and also on the parallel port. On
completion this also causes the event pin to be asserted, so a
transputer process may be scheduled to handle the data where
appropriate. The transputer links are uncommitted: they may be
connected to the NETBUS or the INMOS tree links.
Digital to Analogue Converter
The converter is nominally 10 bits. The value is written to a
particular address in the transputer memory, normally 6140
hexadecimal. The value may be changed at maximum transputer speed.
The analogue output, DAout, will either follow these values or
provide a buffered copy of the external analogue input, XANin. The
choice is determined by the transputer setting a bit, Aout_sel in the
configuration port. XANin is quite separate from the main analogue
input feeding the analogue to digital converter.
Analogue to Digital Conversion
The analogue signal is first terminated and buffered. A high
bandwidth circuit capable of peak sampling then presents samples to
an 8-bit high speed flash converter. The 8 bit digital words are then
delivered into the fast buffer RAM possibly with 'corner-turning'
manipulations. This occurs at the full sampling speed. Standard
boards are fitted with a 32MHz crystal oscillator which gives a
maximum sampling rate of 16MHz. It may be possible to increase this
rate if necessary: the main constraint is the cycle time of the RAMs.
Data is extracted from the buffer RAM either by the transputer
or by an external system using the parallel port. Systems connected
to the external port might include a conventional system or an SIMD
controller. Once the transputer has set up the configuration
correctly, the whole data acquisition and extraction can be
controlled from the external port. To initiate sampling the external
system activates a strobe, GAPgo. The status signal, ACQUIRE, becomes
active. When the number of samples, up to 64K, have been stored,
ACQUIRE becomes inactive. The external system then uses a second
strobe, G_stb, to extract the data. Each sample is presented on the 8
data lines of the external port in response to G_stb. This extraction
can procede at full speed. The exact maximum speed (to be checked)
is better than 60ns.
The transputer enables control of data acquisition from the
external port by setting a bit, GAP_en, in the configuration port. If
this mode is not selected, then the transputer initiates data
acquisition. ACQUIRE is available for the transputer to poll, but the
inverse is connected to the eventIn pin: normally a process will be
scheduled on the event in preference to polling. Such a process may
then read the data from the buffer RAM through another port: this may
occur at full transputer speed.
Peak sampling
If the peak bit is set in the configuration port, then the
maximum value of the analogue input signal is converted and stored in
the buffer RAM. At the start of each sample period (62.5ns when
sampling at 16MHz) the current value of the input is captured. This
initial sampling occupies up to 15ns. It is this value which is
presented to the flash A/D converter if the input signal falls during
the rest of the sample period. However, if the input exceeds this
initial value during the sample, then then the maximum value attained
is digitized.
It may be helpful to note that this peak mode is analogous to
the glitch capture sometimes found on oscilloscopes and logic
analysers.
If the minimum value of a signal is required, the obvious
approach is to invert the analogue input. Failing this, it is simple
to cut two tracks and install two links to achieve a "valley" mode.
When peak is inactive, the system samples the input in a
straight forward way: in fact the value digitized is that at the end
of a sample period, and approximates delta-function sampling.
Corner-turning
Many SIMD machines are composed of an array of bit-serial
processors. Consequently they normally handle data in bit-serial
fashion. The conversion between the bit-serial and the bit-parallel
words used in most other contexts is know as 'corner-turning'.
In the case of 8 bit words, as acquired by ACQSYS, the
successive samples might be A, B, C, and so on. When interfacing with
a conventional machine, these samples will be presented on the
parallel 8 bit port in the usual way: The ith signal carries a bit
Ai, i = 0,1,..,7. But when corner turning is active, the data is
presented on the port in bit serial fashion: the pins might be
presenting A6,B6,C6,... simultaneously. On the next strobe,
A7,B7,C7,... will be delivered. ACQSYS delivers the serial streams
least significant bit first.
When only a small number of bits are required in a calculation,
it is wasteful to deliver all 8 bits in serial streams: that requires
8 clocks. ACQSYS only delivers the 'p' most significant bits when the
'corner-bit' is asserted in the configuration port. 'p' is the
precision, which is determined by the transputer setting the value
into a register. When 'corner-turning' ACQSYS delivers serial streams
each 'p' bits long (p=0 implies all 8 bits).
Few SIMD machines have serial input streams in multiples of 8.
ACQSYS caters for either 6 or 8 serial streams. Yet another bit in
the configuration port, F_Frame, makes the selection. It is obvious
that any mechanism for 'corner-turning' must involve some method of
buffering at least as many parallel words as there are output
streams. If 6 serial streams are to be serviced, then clearly the
relevant 6 time samples must be simultaneously available. For this
reason, ACQSYS acquires data in frames. A frame is simply a group of
6 or 8 samples. A "full frame" is 8 samples and corresponds to 8
bytes of buffer RAM. The buffer RAM consists of 8K frames, and data
acquisition is handled in these units, even when 'corner-turning' is
not used.
OUTLINE
Transputer:
T212 or T222, up to at least 20MHz. 8KB external static RAM, no
wait states.
Interface:
NETBUS and INMOS TREE support.
H_Port:
8 bit data port, 3 control inputs, 1 status, external clock
input. It is possible for the transputer to input data from the 8 bit
port, but its main use is to output acquired data to a conventional
system or to an SIMD system. One control input is used to strobe the
data from this port. Another input may commence data acquisition. The
third allows data input to the transputer. The analogue sampling
clock is taken from this point when a jumper is set appropriately.
The status signal, ACQUIRE, indicates when the required number of
frames have been collected.
XPort
This consists of a 4 bit latched output port with an output
enable, a pulse output, the digital to analogue output with its
ground reference and the extra analogue input. The latched output
port may be bussed: the associated control signal allows it to be
tristated.
TRANSPUTER CONTROL
FAG
Frame Address Generator. This register determines the frame in
the buffer RAM both for data acquisition and extraction. It is
normally set by the transputer before each set of samples is
acquired, and also before data extraction. It may also be read by the
transputer.
FC
Frame Counter. This counter is used only during acquisition. The
transputer writes the number of frames required. When acquisition
starts this counter decrements. When it reaches zero data aquisition
ceases and ACQUIRE becomes inactive. The counter is actually 16 bits
long, but in normal circumstances there is little point in setting a
frame count beyond 8K: beyond this the FAG will wrap around and the
initial 64K samples start to be overwritten.
Config
Configuration Port. 5 bits determine the frequency of analogue
sampling. The basic clock is either the on-board 32MHz oscillator, or
taken from H_Port. This basic clock is always divided by 2 to ensure
that the sample clock has 50% duty ratio. The basic clock may be
further divided by a value from 2 to 16. The 'Corner-bit' determines
whether 'corner-turning' is enabled; Peak activates the peak analogue
sampling mode; F_Frame selects between 6 and 8 serial streams for
corner turning; Gap_en allows acquisition and data extraction to be
controlled from H_Port; APS_en allows the power to the analogue
circuits to be reduced when there is no sampling; Aout_sel determines
the source for the analogue output; and the last bit controls an LED.
Precision
The lower byte of this register is set to the required precision
'p' when 'corner-turning' is enabled. Only the lower 3 bits are used
(p=0 gives 8 bit precision). When 'corner-turning' is inactive, 'p'
may be read to give the byte address within a frame. The upper byte
is used to initiate readback: writing to this register causes
pointers to be set to frame start. Subsequent data extraction will
procede from the first sample in the frame addressed by the FAG. This
write is only necessary after changing the value of 'p' in 'corner-
mode', or if some data in a frame is to be skipped.
ReadBack
Reading this address accesses the byte on H_Port. If H_write, is
held active by an external system, H_Port is an input, and the value
is taken from there. More usually the data is from the buffer RAM. If
GAP_en is inactive the read also causes a state machine to extract
the next byte and place it on H_Port ready for the next read. When
GAP_en is active, the completion of the external read clocks the
state machine.
Buffer Ram
64KB static. Organized as 8K frames. A frame is 8 bytes.
Controlled by fast state machine capable of 'corner-turning' on the
fly. Data may be extracted in 8 or 6 serial streams. When 6 are used,
only 6 bytes in each frame are used, so the buffer is effectively
reduced to 48KB. In all other cases 64KB are available.
Analogue input
Input range: 0 to 2V. Input clamps at approximately -0.6 and
2.4V. Termination normally 50 or 75 ohms. Input buffer: 350MHz
bandwidth. Analogue ground should be within 0.3V of ACQSYS digital
ground diode clamps
A/D converter
8 bits. Max sampling rate approximately 40Msamples/sec. Range: 0
to 2V.
D/A converter
Nominally 10 bits. Better than 0.5 bit in 9 bits. Max conversion
rate approximately 40MHz.
Controls
Reset and analyse buttons. 1 programmable LED.
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