K312240@AEARN.BITNET (Klaus Kusche) (10/22/88)
Dear Mailing List! Here are some news from the Meeting of the German transputer user group on Oct. 17 and 18 in Witten / West Germany. 1.) Parsytec showed its supercluster (64 T's) and boards for the Mac II and the IBM PS/2 series. Moreover, they announced Lisp and Prolog systems for their Hardware as well as GKS. 2.) A German company named SANG showed a PC board (4 T's, 4 MB each), and they announced a Mac II board for 1Q89 and disk and graphics boards for 2Q89. Moreover, they offer link interfaces for the Commodore Amiga and the Atari ST. 3.) A FORTH was rumored (Siemens seems to be behind that). 4.) The Austrian company IMPULS showed their graphics supercomputer: Hardware and performance are very impressive (9 to approx. 400 T's), but I can't tell anything about the software (however, they already showed some real applications). 5.) Peter Eckelmann of inmos Munich presented the future plans for transputer hard- and software (I didn't ask him if I may publish these things, so don't read them, ok?!?). This is also in response to Adrian's request about the breakpoint instruction. T800D: Completely identical to T800C for the user. 25 MHz samples available, 30 MHz samples 1Q89. T425: "T800 without floating point", pin-compatible to T800, T414. Added HW features: * Event waiting output pin: Indicates that the processor has executed an input on the event channel. * Refresh pending output pin: Indicates that the memory interface would like to perform a refresh during external DMA cycles. * Disable Internal RAM input pin: The name says it all. Added SW features: * Load device identity: To support worm programs etc. * Rotate processor stack: The A<->B<->C instruction compiler writers always wanted. * Breakpoint: This is a one-byte instruction ("jump 0", hex 00). Its effect: 1.) Load new context (i.e. Iptr and Wptr) from a fixed two-word location in memory. 2.) Save old context there. 3.) Continue execution in newly loaded context. There are seperate vectors for low-pri and high-pri, they are just above MemStart. This instr is for implementing user and supervisor modes, it is enabled and disabled by a flag which can be set and tested. Moreover, timer interrupts can be disabled by software (to prevent supervisor from being timesliced?). 20 MHz in 1Q89, faster ones "soon". T801: T800 plus all T425 improvements. Seperate data and address bus (like T2), 2 clock ext memory cycle. SW compatible, but not pin compatible (100 pin PGA). 25 MHZ 1Q89, 30 MHz 2Q89. T805: T800 plus all T425 improvements. The traditional memory interface (pin compatible with T800?) 30 MHz 2-3Q89. T222: T212 with 4 KB onchip and fast T8 link technology. 20 MHz samples avail now. T810: Upward compatible with T805 SW, instructions added: Halfword support, character search, ... More priority levels, improved scheduler, one error flag per process. Parallel multiply and barrel shift hardware. Streamlined microcode, many instructions work faster. Better memory interface: Supports VRAMs and page mode (2 clock cycles even on DRAMs). Does RAS and CAS mux. >= 8 KB internal RAM. >= 8 links, perhaps 30-40 Mbit/s. >= 30 MHz. Scheduled for the end of 89 (I don't believe that). T840: The long-term project. The one with link routing and multiplexing support. Nothing known about it yet. B407, B408, B409: Graphics and ethernet TRAMs. D700D: The product release of the TDS (available now). D705B: The product release of the Toolset (full Occam 2, debugger, transputer simulator, make utility) (1Q89). D706A: All the nice TDS utilities (PROMmer, Worm, ...) for the Toolset (1Q89). I hope there have been enough good news for you! Greetings Klaus (K312240@AEARN.BITNET).