J.Wexler@edinburgh.ac.uk (11/23/88)
If you talk to the people who build the Transputer, they (mostly) deny that it is a RISC chip. Most of its instructions follow most of the RISC principles, but a few VERY IMPORTANT ones do not. For all that, the things which are assumed to be the virtues of RISC architecture are broadly true of the Transputer. The virtues are the important thing - whether they are attained by adherence to RISC principles or by some other means is not important. D.Tabak, "RISC Architecture", [ISBN 0 471 91302 2, Research Studies Press/John Wiley, 1987] gave twelve (I think) widely accepted criteria for measuring the RISCness of an architecture. He also evaluated most of the reputed RISC designs available at that time. None of them met all the criteria. The Transputer met more than most. Although it violated a couple of them quite grossly, Tabak reckoned it to be one of the most RISC-like of all the designs. The Acorn ARM chip also got quite a high RISC rating. About on-chip memory: certainly it would be nice for many of us if it were used to support a cache. The reason why it isn't like that on present and earlier generations of Transputers is, I think, because Transputers have another market besides multicomputer concurrency. They are very good for real-time and embedded systems. You can use them to build controllers with a very low chip count. In some cases, the on-chip memory is all you need. The design can be simple; interfacing is easy; power, heat and space are minimal, and the performance is very high. In these applications, it may also be important that the chips are very rugged.