anc@camcon.co.uk (Adrian Cockcroft) (10/13/88)
I just got an update from Rapid Silicon (Inmos distributors) which talks about the new T425. This is based on the T800 but without the FPU so it has 4Kb of on-chip ram and fast (overlapped acknowledge) links. The extra thing that I hadn't heard before was that it has "new break point instructions to enhance debugging". I hope these get added into the T800D as well. Does anyone have any more information on what the instructions will do? Adrian -- Adrian Cockcroft ..!uunet!mcvax!ukc!camcon!anc Cambridge Consultants Ltd, anc@uk.co.camcon or anc@camcon.uucp Science Park, Cambridge CB4 4DW, England, UK (0223) 358855 I am leaving CCL at the end of October 88 to join Sun UK's Cambridge office.
w-colinp@microsoft.UUCP (Colin Plumb) (01/25/89)
For everyone's enlightenment, here's some info from Inmos about the latest transputer goodies. This is all dated mid-last year, but I was never sure if it was proprietary or not. Apparently, is's all clear. So sorry for the delay, but if anyone's interested: ----- T425a ----- Has all the extra T800 features, except the floating-point. It also has all the T414 features (unpacksn, etc.) deleted on the T800. Extra pins: EventWaiting (B3 on PGA, 83 on J-lead) - output, high when a process is doing an in on the event channel. It changes near the falling edge of ProcClockOut; sampling on the leading edge is safe. RefreshPending (A1 on PGA, 82 on J-lead) - output, high when the external memory interface would like to do a refresh, drops low when it does it. It changes state on the rising edge of ProcClockOut; sampling on the faling edge is safe. It always goes high for at least one cycle (when there is no contention), and stays high until notMemS0 goes low on the refresh cycle. You can OR ~RefreshPending in with MemReq from a DMA device to allow the transputer to handle interrupts, but prevent it from making any memory accesses. DisableIntRAM (E1 on PGA, 10 on J-lead) - input, this pin is available all the way back to T414, I believe, but is not documented. When high, it disables the internal RAM, forcing all accesses to appear on the external bus. Useful for debugging with a logic analyser, as you can see interrupts, timer queue activity, etc. Breakpoints: The "j 0" (0x00) instruction can be set as a breakpoint. For backwards- compatibility, this must be enabled by an instruction before the extra functionality becoms available. A lousy compiler could produce this instruction. There is also an instruction to test the status of the breakpoint enable flag. There is a two-byte breakpoint instruction which ignores the enable flag. For each priority level, there are two words in low memory which hold an Iptr and a Wptr. When the breakpoint is hit, the running process' Iptr and Wptr are swapped with those stored. Areg, Breg, and Creg are unchanged. Note that the same instruction can be used to take the breakpoint and return. Or use the two-byte instruction if you wish to disable future breakpointing. The words are just above MemStart: 0x8000007C (0x1F words) Iptr (low priority) 0x80000078 (0x1E words) Wptr (low priority) 0x80000074 (0x1D words) Iptr (high priority) 0x80000070 (0x1C words) Wptr (high priority) Other new instructions: rot: this rotates the processor stack, Areg->Creg, others popped. This can also be used as a drop. fptesterr: this always returns 1, and is guaranteed to work to make it easier to use T800 startup code on the T425. ldmemstartval: this returns MemStart in Areg. lddevid: this returns the type of the transputer it's running on. It is a NOP on the T212a, T222c, T414a, and T414b. On the T800b through T800e, it trashes Areg and pops Breg into Creg. On the T425a, it pushes 0 onto Areg. The suggested usage is "ldc -1, ldc -2, ldc -3, lddevid." If you then rev, it will return -1 on a T800, -2 on an earlier chip, and -3 on a later chip, such as the T425. The second word will tell you the identity of the later chip. I presume you can figure out a way to tell a T414 and T212 apart. timer(disable|enable)(l|h) - this family of four instructions can temporarily disable the timer interrupts for the two priorities. They're useful if you want to mess with the queues directly and don't want anyone else touching them. The links are still a problem. start - this is the transputer's reset instruction, which it executes when you let go of the reset line. On the T425, it clears all the flags (Error, HaltOnError, and EnableJ0Break) instead of leaving them alone, as earlier transputers did. Analyse leaves them unchanged. Inmos sent a description of this instruction around, but documented the opcode as 0x2FF. WRONG. THE OPCODE IS 0x1FF, LOW NINE BITS SET. Instruction opcodes and timings: j 0 0x0 3 cycles (break disabled) j 0 0x0 11 cycles (break enabled, high priority) j 0 0x0 13 cycles (break enables, low priority) break 0xB1 9 cycles (high priority) break 0xB1 11 cycles (low priority) clrj0break 0xB2 1 cycle setj0break 0xB3 1 cycle testj0break 0xB4 2 cycles (Areg gets 1 if enabled, 0 if diabled) rot 0x79 1 cycle (Creg->Breg->Areg->Creg) timerdisableh 0x7A 1 cycle timerdisablel 0x7B 1 cycle timerenableh 0x7C 6 cycles timerenablel 0x7D 6 cycles ldmemstartval 0x7E 1 cycle (push constant 0x80000070) fptesterr 0x9C 1 cycle (push constant 1) lddevid 0x17C 1 cycle (push constant 0) start 0x1FF ? cycles (lots) ----- T801 ----- This is the non-multiplexed-bus T800, to achieve 2-cycle EMI interfaces. It will be in a 10x10 100-pin package, and they've shrunk the process, so parts may go to 30 MHz. There are some timing diagrams I don't quite understand, but they have a "notMemCE" pin that goes low a quarter of a cycle (12.5 ns at 20 MHz) after the start of T1 (there are only 4 Tstates), seemingly indicating valid addresses, and goes high as quarter of a cycle before the end of T4. Data has 45/38/30 ns at 20/25/30 MHz to set itself up. A number of EMI features got sacrificed. You can't get 5MHz links; Link0Speed and Link123Speed select 10 or 20 Mbits/sec. The high two bits got chopped off the address bus, etc. Anyway, the pin counts are: Address2-29 28 Data0-31 32 Analyse 1 ErrorIn 1 ErrorOut 1 Reset 1 BootFromRom 1 ClockIn 1 CapPlus 1 CapMinus 1 ProcSpeed 3 Link0Speed 1 Link123Speed 1 LinkIn0-3 4 LinkOut0-3 4 EventReq 1 EventAck 1 EventWaiting 1 ProcClockOut 1 notMemWrB0-3 4 notMemCE 1 MemWait 1 MemReq 1 MemGranted 1 Vdd 2 Gnd 5 ----- T810 ----- This is still in the works, and I have basically a list of ideas. It has advanced considerably since this, but I don't know many details. The process should provide parts out to past 30MHz. It will have: Object-code compatibility with the T800 Large internal RAM (8K to 32K) High-speed & flexible EMI Configuration via memory-mapped registers Added CPU features Faster CPU and better microcode Eight (8) links Faster links 340 or 40 MHz) EMI: 32 data pind, 16 address pins Multiplexed RAS/CAS addresses and VRAM support Uses DRAM page mode 4 independent DRAM banks [I dunno quite what this means] Bank address allocation and memory protection [? but !] 2 cycle accesses at 30 MHz Speedups - some ideas: 1-cycle ldl, stl, ldnl, stnl 1-cycle lb, sb [yeah!] 1-cycle eqc, gt [yeah!] Fast multiply and shift [yeah!] Faster block move startup Faster scheduling [yeah!] New instructions - some ideas: Fast loop with only one index 16-bit load & store (for C) Null-terminated string handling Unsigned greater than [yeah!] Constant value block fill [yeah!] Linear interpolation (Gouraud/Phong shading) [?] Bresenham's algorithm (DDA for line drawing) [?] Byte-wide saturating addition for R-G-B-alpha 32-bit pixels [? but maybe !] Error state per process and errant process queue [This is for sure - and I like it!] Disable and enable of link interrupts [useful with T425 features] I imagine all the T425 features will be there, but it's not mentioned. -- -Colin (uunet!microsoft!w-colinp)