braner@batcomputer.tn.cornell.edu (Moshe Braner) (02/22/89)
[] One disadvantage of using a 2-layer C004 switching network is that, going through 3 C004's in a row, the data transfer rate on the link is reduced by a half (from about 1.8 MBytes/sec to 0.9). At least that's the case on our Niche board (T800-20s). I have it on good authority that using only 1 or 2 C004s on one link does not have this affect: the acknowledge bits get back just in time. Did anybody try that? Is there any solution for the layered approach (e.g. faster switch-chips)? - Moshe
Trevor_Carden_THORN_EMI_CRL@ie.ucd.eurokom (02/22/89)
James Pinakis asks: >I'm interested in any references anyone may have on the C004. In >particular, has any work been done using C004s to dynamically >reconfigure a transputer network according to workload distribution? We have considered using C004 switches for dynamic switching during the development of the Parsys SN1000 Series of transputer `Supernode' machines. In order to reconfigure the switches in an efficient manner, we have had to provide several other hardware features. The main design target was to provide a link switching network that would guarantee that any transputer network could be implemented in a simple and predictable way. Some switching networks that have been implemented in transputer systems are hard to analyse mathematically, making the task of mapping a network onto the switch difficult. Even for a static link network, non-deterministic algorithms requiring extensive computation have been used but do not guarantee a result. Such an approach is not suitable for supporting dynamic reconfiguration. The switch architecture that was developed with our collaborators under European ESPRIT project 1085 has the following features: transputers are clustered together in Supernodes where all link switching is performed by a single layer of switching. To connect two transputers within a Supernode, a single switch setting command is required so that the links may be connected quickly. In order to increase the number of transputers that could be connected in this fashion above the limit of 32 for a C004, a special switch chip was developed providing switching for 72 transputers. For larger systems, several Supernodes may be connected together. A three layer switch is used to minimize the number of switch setting commands that have to be issued to make a connection. If a connection is required between transputers in different nodes, the 72 way switches in each Supernode are used to connect the transputers to inter-node links; these two inter-node links may then be connected through a C004 in the Inter-node Switch. This arrangement may be used to support over a thousand transputers with a very simple switch setting algorithm that guarantees that all possible transputer networks may be set up (see Switching Networks For Transputer Links by D. Nicole et al. in the Proceedings of the 8th Technical Meeting of the Occam User Group, Sheffield, ed. J. Kerridge, 1988). The 72 way switch is memory mapped on a Supernode Controller transputer, while the Inter-node Switch is controlled through an array of T212 transputers that each control two C004 chips. This allows fast control of all the switches within the system. Other C004 switches are used for connecting to peripheral devices, but do not require high bandwidth reconfiguration - these are driven by memory mapped link adapters on the Supernode Controller transputer. There is a disadvantage of using the C004 in a fully switched link network. The C004 reset state has all outputs disabled, so all links are isolated. Before communications can take place with the outside world, it is necessary to configure the C004s, either with boot-from-ROM code on the switch controllers or by providing a state machine that pumps commands into the C004s after reset. It would be useful to have some default connection options present in future C004s, or a non-hand-shaken configuration pin that can be used to pump in an initialization state after reset. Before dynamic switching can be performed, the two ends of a link must be placed in the idle state to avoid message corruption. The Supernode has a separate communications network, called the Control Bus, to provide support for this. Before the Switch Controller alters a link network, it can suspend communications on the affected links by passing messages on the Control Bus to all affected transputers. The worker transputers may also request switch changes by passing messages to the Switch Controller. The Control Bus has additional facilities to allow synchronization between multiple transputers. When a group of processors have all reached a certain state, a message can be passed to the Switch Controller to indicate that all of the transputers have finished communication over a link network. The Switch Controller can then rearrange the network and signal that communications may resume. This allows a PLACED PAR within SEQ construct in Occam to be supported efficiently and is useful for processor communications within a multi-processor Unix environment. ----------------------------------------------------------------------- Trevor Carden (01 or +44 1) 848 6504 Parsys Ltd., THORN EMI CRL Dawley Road, Hayes, Middlesex, UB3 1HH, England Trevor_Carden_THORN_EMI_CRL%eurokom.ucd.irl@euroies.uucp
Trevor_Carden_THORN_EMI_CRL@ie.ucd.eurokom (02/24/89)
Moshe Braner <braner@TCGOULD.TN.CORNELL.edu> comments: >One disadvantage of using a 2-layer C004 switching network is that, >going through 3 C004's in a row, the data transfer rate on the link >is reduced by a half ... >Is there any solution for the layered approach (e.g. faster switch-chips)? The C004 provides link switching and also clock resynchronization to avoid signal skews adding up from one switch to the next. It is this resynchronization that causes the delay of about 1.75 bit periods when passing through each C004 in each direction. It would be very difficult to reduce this in a new C004 design while still providing resynchronization that is able to tolerate slightly different clock rates at each end of a link. In the ESPRIT Supernode project in which the Inmos T800 and the Parsys SN1000 series were developed, much attention was paid to providing a two layer switch architecture that would not impose significant bandwidth restrictions on the link traffic. The overlapped acknowledge of the T800 links was introduced to allow at least one clock resynchronization to occur along a link connection without affecting bandwidth. In addition, no clock resynchronization is used in the 72 wide Supernode link switch, so only a small propagation delay of a fraction of a bit period occurs. The second layer switch for making Inter-node connections from one Supernode to another does use C004 switches, and hence preserves signal quality. Using this combination, a two layer switch can be built that does not affect link bandwidth and allows simple configuration of any transputer network. Large systems of over 1000 transputers can be supported in this way, though the physical size of such a system makes additional buffering and resynchronization necessary for Inter-node connections. These extra buffers make the Inter-node link delay similar to that in a system using two layers of C004 switches. However, a wide switch at the Supernode level was chosen so that each Supernode contains as many transputers as possible. The number of link connections that have to pass through the Inter-node switch is therefore minimized, allowing most links to operate at full bandwidth. ----------------------------------------------------------------------- Trevor Carden (01 or +44 1) 848 6504 Parsys Ltd., THORN EMI CRL Dawley Road, Hayes, Middlesex, UB3 1HH, England Trevor_Carden_THORN_EMI_CRL%eurokom.ucd.irl@euroies.uucp