MJP@vaxb.roe.ac.uk (10/04/89)
In a recent article, Kevin Bertram writes: > I have a problem with the C012 Link adapter which the product >data sheets don't have an answer for. And I thought that maybe someone >here, in this news group, could answer it for me. > On the C012 Link adapter chip pin 14 has the function of >"SeperateIQ". What does this pin do and what should its logic state be >for normal functioning of the chip? The block diagram of the chip towards >the front of the data sheets don't include this pin name and the pin name >description list has forgotten it too. > One more thing. The "CapMinus" line connects to the "Minus" side >of a capacitor but where does the positive side go? Is it safe to assume >Vcc? > > Thanks for any help you might have. > > -Kevin (kevin@latcs1.oz) > The data sheet I use (printed in the Transputer Databook, First Edition 1989) indicates that pin 14 has the function HoldToGND, NOT SeparateIQ. However, SeparateIQ on the C011 (pin16) selects Mode 2 when connected to GND, Mode 1 10 Mbits/s when connected to Vcc, and Mode 1 20 Mbits/s when connected to ClockIn. The capacitor positive end does go to Vcc. Cheers, *************************************************** Magnus Paterson, * janet - mjp@uk.ac.roe.vaxb * Royal Observatory, * cbsmail - cbs%uk.ac.roe.vaxb::mjp * Edinburgh * earn - mjp@vaxb.roe.ac.uk * Scotland * arpa - mjp%vaxb.roe.ac.uk@nss.cs.ucl.ac.uk * * arpa - mjp%vaxb.roe.ac.uk@ukacrl.bitnet * If all else fails, * span - 19463::revad::mjp * ph. 031-668-8247 * starlink - revad::mjp * fax 031-668-8264 * psimail - psi%000007002002::mjp * * janet - mjp@uk.ac.roe.star * ***************************************************