dil@lfcs.ed.ac.uk (David Laurenson) (11/10/89)
I am trying to build a transputer link analyser that passively
monitors the communications link between two transputers, and produces
a high level (hopefully) form of debugging/performance monitoring. I
am currently trying to find a suitable differential driver/receiver
pair that I can use that will not introduce more than 3nS skew.
I am currently looking at the uA9637AC and uA9638C pair, but I am
unsure of their skew tolerance. Has anyone already buffered the
links successfully, and if so what chips did you use?
David I. Laurenson |
Department of Computer Science |
Edinburgh University King's Bldgs | JANET dil@uk.ac.ed.lfcs
Mayfield Road, EDINBURGH U.K. |hjm@cernvax.UUCP (Hubert Matthews) (11/13/89)
In article <1049@castle.ed.ac.uk> dil@lfcs.ed.ac.uk (David Laurenson) writes: >I am trying to build a transputer link analyser that passively >monitors the communications link between two transputers, and produces >a high level (hopefully) form of debugging/performance monitoring. I >am currently trying to find a suitable differential driver/receiver >pair that I can use that will not introduce more than 3nS skew. Can someone from INMOS please tell me why the skew spec for 20 Mbits/sec is so tight? 6% of a bit makes things very difficult for link buffers as the above user has discovered. Why does the skew become more important at higher rates? 30 ns @ 5 Mbits/sec, 10 ns @ 10 Mbits/sec and 3 ns @ 20 Mbits/sec seems like a strange relationship to me. Using INMOS link switches, which do bit regeneration, is obviously the thing to do, but these *do* slow down transfers, despite what the documentation says. -- Hubert Matthews ...helping make the world a quote-free zone... hjm@cernvax.cern.ch hjm@vxomeg.decnet.cern.ch ...!mcvax!cernvax!hjm
lindsay@watnext.Waterloo.EDU (Lindsay Patten) (11/14/89)
In article <1049@castle.ed.ac.uk>, dil@lfcs.ed.ac.uk (David Laurenson) writes:
: I am trying to build a transputer link analyser that passively
: monitors the communications link between two transputers, and produces
: a high level (hopefully) form of debugging/performance monitoring. I
: am currently trying to find a suitable differential driver/receiver
: pair that I can use that will not introduce more than 3nS skew.
:
: I am currently looking at the uA9637AC and uA9638C pair, but I am
: unsure of their skew tolerance. Has anyone already buffered the
: links successfully, and if so what chips did you use?
I'm probably being niave but, would C011 chips make this sort of thing
fairly easy? I have to admit that I don't know what perfomance loss
they cause.
Lindsay Patten "People are package deals - No substitutions allowed"
Pattern Analysis & Machine Intelligence Group lindsay@watnext
Department of Systems Design Engineering lindsay@watnext.waterloo.edu
University of Waterloo {utai|decvax|uunet}!watmath!watnext!lindsay