JAAP@utwente.NL (11/24/89)
Hello mailing list, As we all know, the data entering a transputer (or another transputer link compatible device) via a link, is not synchronized with the internal clock of that device. The device has to synchronize the incoming data with its internal clock before these data can be processed. For the design of an IC with transputer link compatible inputs, we would like to know how this problem is solved in the hardware of a transputer, or how people think that this problem is solved or could be solved. We think that we have found a good solution, which can be implemented easily. However some other opinions about this topic would be welcome. Of course we would be glad to discuss our solution with interested people. Thanks in advance, Jaap. Jaap Hofstede Dept. Computer Science (INF/SPA) University of Twente PB 217 7500 AE ENSCHEDE Netherlands Tel: +31 53 893788 Email: JAAP@HENUT5.NL
derek@cs.qmc.ac.uk (Derek Coppen) (11/24/89)
Transputers use a PLL to generate a high frequency clock (100MHz I believe) to time in the serial data just the same as a conventional UART. In my application I wanted to connect a link adaptor to an Ethernet controller. The INMOS link adaptors at 20Mbaud don't go fast enough to support a 10Mbaud ethernet link partly because of the frame overhead and servicing latency, but mainly because the adaptors don't support the overlapped acknowledge protocol. My solution was to implement a double buffered overlapped ack link adaptor on a Xilinx LCA chip using both edges of a 40MHZ crystal clock instead of the 100MHz PLL source. There was enough room left on the chip (the smallest in the range) to implement a finite state machine to control a 9 bit bidirectional data bus with read and write strobes to the Seeq8003 ether controller. As a bonus a 20MHz output feeds the manchester encoder saving an extra crystal.