[comp.sys.transputer] H1 transputer

abs@ukc.ac.uk (A.B.Smith) (11/30/89)

In article <IZQx_kG00WB382fmY3@andrew.cmu.edu> js7a+@andrew.cmu.edu (James Price Salsman) writes:
>STORZ@EMBL.BITNET writes:
>Only 2K instead of 4K.
>
>Nope, only TWO!!!  Kinda defeats the purpose.  The H-1 is
>definetly going to be a linear array.
>

The T400 has 2K on-chip RAM, 2 links, etc.

There seems to be some confusion between the H1 and the T400. This is a
copy of the ***INMOS*** 'Product Update' published in the SERC/DTI
Transputer Initiative Mailshot (November 1989). And I beleive this is the
only official information INMOS have released.

Enjoy :-)

Andrew. (typing mistakes are mine).

Next Generation - H1
--------------------

The next generation of transputer is under development now and is
codenamed "H1". Silicon is scheduled for 1Q91 and we have released some
preliminary bullet points to give an indication of the performance and
features we are planning.

- Code compatable with T800. H1 will be able to run all your existing
  software, making system updates very simple. You will also be able to
  build systems with mixed H1 and T2/T4 or T8 processors.

- Performance will be greater than 100 MIPS and 20 MFLOPS on a single
  processor giving over five times the performance of existing t800-20
  products.

- The on-chip memory will be enlarged and operated as on-chip cache to
  support the performance levels indicated above.

- The external memory interface will continue to offer a programmable
  minimum chip solution for DRAM, SRAM and EPROMs. It will include all the
  logic required to support new features such as static column and page
  mode DRAMS.

- The serial links on the transputer will support a higher rate and
  conform to a new protocol to increase communications bandwidth.

  There will also be hardware support for virtual channels and message
  passing, thus making the design of networks of transputers more
  effective and efficient.

  There will be an interface chip so that the new links can be connected
  to existing link technology.

Further information will be released on this exciting new product during
the first half of next year.
-- 

Andrew B Smith
Computing Laboratory, The University, Canterbury, Kent. CT2 7NF, UK
Telephone: (0227) 764000 ext: 7684; JANET:  abs@UK.AC.UKC