K312240@AEARN.BITNET (Klaus Kusche) (11/29/89)
Dear Mailing List: The only definite (printed and Inmos-authored) information I've ever seen about the new H1 transputer appears in the SERC/DTI Mailshot, issue November 1989, page 10. Is there any possibility that someone who has that stuff in electronic form posts it on the list??? As usual (?!?), the information is quite short and does omit all details, there is nothing in it which you wouldn't trivially expect. Just one question about that announcement (is expected to be answered by Inmos people!!!): The first item there promises "Code compatible with T800. H1 will be able to run all your existing software, ..." Does this really mean that all binaries, even those not produced by the TDS or other Inmos compilers, will run unchanged, even if they contain all kinds of handcrafted assembler tricks??? This would also imply that the memory map, the link interface, the queue organization and of course the register set are the same or at least compatible... Too good to believe! Any comments about it? I think what they actually meant is source code compatibility: Just buy their new compilers and recompile all your stuff.... Greetings ************************************************************************ * Klaus Kusche * * Research Institute for Symbolic Computation * * Johannes Kepler University Tel: +43 7236 3231 67 * * A-4040 Linz Telex: (Austria) 22323 uni li a * * Austria (Europe) Fax: +43 7236 3231 30 * * * * Bitnet: K312240@AEARN * * Arpa/CS/Internet: K312240%AEARN.BITNET@CUNYVM.CUNY.EDU * * UUCP: mcvax!aearn.bitnet!K312240 * * Janet: k312240@earn.aearn or k312240%aearn@earn-relay * ************************************************************************
STORZ@EMBL.BITNET (11/29/89)
In article <8911281522.AA26703@tcgould.TN.CORNELL.EDU>, Klaus Kusche <K312240%AE ARN.BITNET@tcgould.TN.CORNELL.EDU> writes: > > The only definite (printed and Inmos-authored) information I've ever > seen about the new H1 transputer appears in the SERC/DTI Mailshot, > issue November 1989, page 10. The information I have read (SGS-Thomson-Cheft Pistorio) announced the H1 as - full command compatible to t4/t8 transputers (???) - 100 MIPS/20 MFlops - at least 18 months from now - fighting for the embedded market Anywhere else I have read (sounds like ideas, not yet fixed) - virtual links (routing in hardware) - internal RAM (used like before or switched as fast CACHE) - commands for fast 'standard' languages like C - (perhaps MMU ???) Somewhere else I heard about 6 links ? No garanty for that informations. Clemens Storz EMBL Heidelberg
js7a+@andrew.cmu.edu (James Price Salsman) (11/29/89)
STORZ@EMBL.BITNET writes: > - virtual links (routing in hardware) Yes. Keeping this backward-compatible is going to require stressful contortions on the part of many designers... > - internal RAM (used like before or switched as fast CACHE) Only 2K instead of 4K. > - commands for fast 'standard' languages like C Dunno. I sure hope they come up with somthing faster than the "lend" instruction for tight inner toops, though. > - (perhaps MMU ???) Yes, designed to run Unix. Also static column mode DRAM addressing. > Somewhere else I heard about 6 links ? Nope, only TWO!!! Kinda defeats the purpose. The H-1 is definetly going to be a linear array. The funny thing is that it seems very much like the iWarp being developed here. I'm soooo confused. ----- :James Salsman (js7a+@andrew.cmu.edu) ::Carnegie Mellon
stein@dhw68k.cts.com (Rick 'Transputer' Stein) (12/02/89)
In article <8911282053.AA06866@tcgould.TN.CORNELL.EDU> STORZ@EMBL.BITNET writes: > >The information I have read (SGS-Thomson-Cheft Pistorio) announced >the H1 as > - full command compatible to t4/t8 transputers (???) > - 100 MIPS/20 MFlops > - at least 18 months from now > - fighting for the embedded market > > - virtual links (routing in hardware) > - internal RAM (used like before or switched as fast CACHE) > - commands for fast 'standard' languages like C > - (perhaps MMU ???) > >Clemens Storz My sources (who will remain entirely anonymous) have stated the following data: - 100 MIPS - 4 bi-directional links @ 10 MBytes/s per direction - virtual channels (potentially worm-hole thru-routing) - 15 MFlops Linpac - 30 - 50 MHz clock rate (Guess which clock for above figures) - 168 pins (maybe 144) - 16 KByte on-chip fully associative cache - two external memory configurations selectable thru on-chip registers - SRAM - 20 bit address bus + 32 bit data bus - DRAM - 16 bit address bus (RAS/CAS multiplexing done on-chip) - 32 bit data bus - 4 banks of interleaved DRAM - each bank can be page mode or static column mode accessed - can directly drive up to 16 MBytes DRAM - improved interrupt handling - multiple priority levels? - instruction set compatible with existing transputers -- Richard M. Stein (aka, Rick 'Transputer' Stein) Sole proprietor of Rick's Software Toxic Waste Dump and Kitty Litter Co. "You build 'em, we bury 'em." uucp: ...{spsd, zardoz, felix}!dhw68k!stein