yule@prl.philips.co.uk (ANDREW YULE) (02/27/90)
Does anyone out there know anything substantial about the iWARP?
I'm doing a general survey and can't get anything but rumours.
Thanks in advance
Andy Yule (yule@prl.philips.co.uk)beers@tputer.tn.cornell.edu (Jim Beers) (02/27/90)
I was just ready to ask just this question. I would be interested in what you find out. I am told that H. T. Kung of Carnegie-Mellon has a biblio on systolic arrays, including references to the iWARP. He was not yet returned my e-mail, his address is ht.kung@a.cs.cmu.edu Or so I'm told. Jim Beers Advanced Computing Research Institute Cornell Theory Center.
Jon.Webb@CS.CMU.EDU (03/01/90)
Here are some iWarp references. ``iWarp: An integrated solution to high-speed parallel computing,'' Borkar et al., Proceedings of the Supercomputing Conference, Orlando, FL 11/88. ``Architecture and compiler tradoeffs for a long instruction word microprocessor,'' Cohn, Gross, Lam and Tseng, Third Int'l. Conf. on Architectural Support for Programming Languages and Operating Systems, Boston, 4/89. ``Network-based multicomputers: redefining high performance computing in the 1990s,'' Kung, Decennial Caltech Conf. on VLSI, Pasadena, CA 3/89. Intel also has a lot of other information for distribution. As of yesterday, the component was running single-cell code and also sending its first messages to other components. For further info on iWarp contact Intel Corporation iWarp marketing, MS JF1-60 5200 Elam Young Parkway Hillsboro, OR 97124 (503) 696-4746 -- J
ENGLE@A.ISI.EDU (03/29/90)
Some specs on the iWarp: - Two modes of communication: message-passing, or systolic. - Four communications links each capable of 40MBytes/s each. - On-chip communications agent which supports cut-through and worm-hole routing in hardware. - 20MFlops floating point performance. - 20MIPS integer performance. - Large instruction word format. - 64-bit memory access. - On-chip bug/break features. The communications agent operates in two modes, message-passing or systolic. In message-passing the system supports hardware routing of multiple logical connections per physical connection. In systolic mode, the processor supports a dataflow style communications in which the removal of an operand from the stream allows the next operand to move up in the stream. These operands go directly into the CPU registers where they can become part of a computation and be placed back into the stream with very little delay. The computation agent contains seperate units for integer, floating-point, and streaming/spooling. All of these units have access to a 15-port register file with 128 32-bit locations, accessible as bytes, half-words, or double words. All of these units can operate independently of other units on the chip. The register unit is capable of nine read and six write operations in a single clock period. The streaming/spooling unit handles the storage of incoming data into memory. This chip is a serious contender against the transputer. It is currently being marketed toward signal processing applications, but its not hard to see the applications in transputer-like workstations. Steven W. Engle Senior AI Software Engineer MIMD Systems, Inc.