mwebster@undeed.UUCP (Mitchell R Webster) (07/24/90)
Does anybody know the specified phase relationship between the 5 MHz input clock to the transputer and its ProcClockOut ? Perhaps a friendly IMOS employee or two could respond. This information doesn't appear in the data sheets. Please reply to email address or fax/mail diagrams, drawings etc to : Duncan Woodward Transputer Applications Group Electrical Engineering Dept. University of Natal King George V Ave Durban 4001 South Africa Thank You.
davidb@brac.inmos.co.uk (David Boreham) (07/26/90)
In article <1049@undeed.UUCP> mwebster@undeed.uucp (Mitchell R Webster) writes: > >Does anybody know the specified phase relationship between the 5 MHz input >clock to the transputer and its ProcClockOut ? Perhaps a friendly IMOS >employee or two could respond. This information doesn't appear in the data >sheets. Please reply to email address or fax/mail diagrams, drawings etc to Easy answer: There isn't one. Not that's worth looking for anyway. If you want to, mail me describing what you are thinking of doing and I'll see if there is another way, such as putting the device in PLL disable mode. David. David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb Bristol, England | (us): uunet!inmos.com!davidb +44 454 616616 ex 547 | Internet: davidb@inmos.com