news@prg.ox.ac.uk (news) (10/04/90)
I can't say I really believe this sort of thing, but since Lindsay Patten
asks (in article <1990Oct2.204634.16609@watserv1.waterloo.edu>), at the York
OUG meeting the Inmos stand was (at least at the beginning of the meeting)
knee deep in uninformative eight-page leaflets called the H1 transputer
`product preview'. It really is pretty uninformative, but I can safely assume
that it isn't covered by any pledges in blood that I may have made to anyone.
The cover says:
Instruction set compatible with the IMS T805
[ that seems to mean `binary compatible' and the compatibility mode
running is on a per-process basis
]
Pipelined superscalar micro-architecture
Workspace cache
4Gbyte physical address space
16Kbyte instruction and data cache
>150MIPS peak
>60MIPS sustained
>20MFLOPs peak
>10MFLOPs sustained
Sub-microsecond interrupt response
[ this may be code for `more register banks for fast swaps' ]
Per process error handling
Enhanced support for pre-emptive schedulers
[ or perhaps that is the line that is code for `more register banks' ]
Memory protection and address translation
Virtual channels
Support for message routing
80Mbytes/s total bi-directional link bandwidth
[ there are four links, four events, and two control links
shown on the block diagram alongside
]
Separate control system
Single 5MHz clock input
50MHz internal clock
Single +5+/-5% power supply
The rest of the document (everything says `preliminary' and `we don't promise
anything', and is dated September 1990) is, I am told, largely unintelligble
unless you already know what it means. Oh, I exaggerate. I'm just trying to
get out of typing it all in. I guess the only other thing to say is that all
of the links (even the control system links) are of the four-wire style that is
being used for the H series communications. There is a C100 link converter
which is meant to be out before the H series transputers themselves.
They weren't promising anything. Neither am I; errors and imaginings excepted.
g