kevin@latcs1.oz.au (Kevin James Bertram) (10/11/90)
I have a question concerning the Transputer of which no answer
has become obvious through either the data sheets or normal contact.
The problem is: should the ERROROUT signal of any of the CPU's get reset
to an inactive state after a reset. (not analyse state)?
This is assuming that the CPU does not have an ERRORIN
input, or if it did then it is at a inactive state.
I ask this because my experience says it doesn't. At least with the T8's
and T414's. BUT T400 do clear their ERROROUT line on reset. So which is
true? Is it luck that the T400's do reset ERROROUT?
Thanks.
-Kevin (kevina@latcs1.oz)davidb@brac.inmos.co.uk (David Boreham) (10/15/90)
In article <8972@latcs1.oz.au> kevin@latcs1.oz.au (Kevin James Bertram) writes: > >I ask this because my experience says it doesn't. At least with the T8's >and T414's. BUT T400 do clear their ERROROUT line on reset. So which is >true? Is it luck that the T400's do reset ERROROUT? Jumped the gun a bit on the previous reply. All new devices which have breakpointing features (T225,415,400,805) DO reset the error flag when the hardware is reset. Other devices (T800, T414, 222) DO not. David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb Bristol, England | (us): uunet!inmos.com!davidb +44 454 616616 ex 547 | Internet: davidb@inmos.com
kevin@latcs1.oz.au (Kevin James Bertram) (10/16/90)
It's been a week since I had asked if the ERROROUT signal of the Transputer is cleared on reset. Unfortunatly there were no answers. I'll rephrase the question in hope of an answer. Does a reset sequence clear the ERROROUT signal (appears on pin 1D of a PGA package) and also the ERROR flag within the CPU? The reset pulse that appears on pin 3E follows a low-high-low transistion with a duration of about 300 ms. ERRORIN (if supplied on the chip) on pin 3D is low, ANALYSE is low (pin 2F). The CPU type can be anyone of the Transputers available. -Kevin (kevin@latcs1.oz)