R.Peel@ee.surrey.ac.uk (Roger Peel) (01/03/91)
The World's Leading Conference on Multiprocessing
TRANSPUTING '91
22 - 26 April 1991
Sunnyvale Hilton Inn, California
Transputers are the revolutionary microprocessors for multiprocessing which
have outsold all other 32-bit RISC architectures. They are fuelling explosive
growth in science and engineering by extending the ability to solve complex
problems fast, elegantly and at reasonable cost.
Highlights of TRANSPUTING '91 will include :
* A complete technical disclosure of the next generation INMOS H1 transputer,
which will offer 150 MIPS and 20 MFLOPS peak performance, as well as
enhanced support for multiprocessing and interprocessor communications.
* Five invited speakers from the U.S.A., the U.K. and Japan.
* 67 contributed papers, fully-refereed and selected to present a wide range
of parallel processing techniques, applications and experiences.
* A wide ranging tutorial program which will be invaluable as an
introduction to multiprocessing hardware and software techniques, to
show how transputer technology may be used to support specific
application areas, and how transputers can play an important part in
the teaching of concurrency and parallelism.
* The opportunity to meet experienced transputer users drawn from
every continent, to discuss how multiprocessing can simplify the design
of your applications and how to get started.
* Exhibitors sponsoring the conference include SGS-THOMSON Microelectronics,
ESPRIT, Parsytec, Paracom, Parasoft, Transtech Devices, JMI Software,
Yarc Systems Corporation, Distributed Software Ltd, 3L, with others
to be confirmed. Non-commercial demonstrations of transputer applications
will also be present.
TRANSPUTING '91 builds upon the previous successful meetings of the
many Transputer and Occam User Groups worldwide, and is being organized
by representatives of these Groups - the World Transputer User Group
Committee.
The World's Leading Conference on Multiprocessing
=================================================
If you're investigating the use of parallel or multiprocessing in any
application, be sure not to miss TRANSPUTING '91. This international event
includes five days of selected presentations, tutorials and workshops on
the powerful concepts of parallel computing based upon communicating process
architectures, and will feature a full technical disclosure of the
next generation transputer, codenamed H1.
Invited speakers include representatives from Fujitsu Labs, Harvard
University, and IBM's T.J.Watson Research Centre. A concurrent exhibition
will support the conference themes of performance and scalability, porting
existing systems, parallelization paradigms, formal methods and security,
programming languages, support environments, standards, and applications.
Applications discussed and demonstrated at TRANSPUTING '91 will include
embedded real-time systems, workstations, supercomputers, laser printers,
disk arrays, image processing, global positioning by satellite, artificial
intelligence, databases, and the testing of scientific and mathematical
theories.
So... plan to find out what transputing is all about. See state-of-the-art
application demonstrations and product exhibitions from around the world.
Gain an in-depth understanding of the new software and hardware technologies
enabled by the transputer. Discover H1. Learn why transputers make sense -
today and for the future.
Endorsers of this conference include:
=====================================
* ESPRIT
* The Institute of Physics
* The Institute of Electrical Engineers
* The British Computer Society
* The Parallel Processing Connection
* The New Zealand Computer Society
* The Oregon Advanced Computing Institute
* The Edinburgh Parallel Computing Center
and others
Special Invited Speakers
========================
Mr. Riichirou Take and Mr. Yasuo Noguchi
Researchers, Artificial Intelligence Laboratory, Fujitsu Laboratories Ltd.
"An architecture for parallel database computing"
The paper proposes an MIMD computer aimed at database processing and
general purpose applications. An experimental system has been made using
32 T800s as processing nodes and 32 for Dragon Net, a binary n-cube
structured network which can optimally process all-node-to-all-node
communication based on a simple rule.
Mr. Take and Mr. Noguchi are researching into concurrency control for
distributed database management systems, and parallel architecture and
algorithms for speeding up database operations. Mr. Take has a degree in
Mathematical Engineering and Information Physics from the University of
Tokyo. Mr. Noguchi has a Masters degree in Pharmaceutical Science from
the University of Tokyo.
Mr. Jonah McLeod
Editor, Electronics
"An industry-wide perspective on parallel and multiprocessing"
Jonah McLeod has been with Electronics and Electronic Design since 1979,
writing on the whole spectrum of electronic equipment. Prior to this he
managed the Apple Computer and Intel Corp. accounts at Regis McKenna PR,
before which he was west coast editor of Computer Design. He has written
several books on computers, computer peripherals and CAD, and has a
Bachelor of Science from the University of Texas.
Dr. David May
Manager, Transputer Architecture and Development, INMOS
"Towards general purpose parallel computers"
David May is currently working at INMOS on the architecture of a new
product range for introduction in 1994. He graduated from Cambridge
University with a degree in Computer Science and has published about 45
papers and 15 patents. He is Visiting Professor of Engineering Design at
Oxford University and has an honorary DSc from Southampton University for
his contributions to the development of parallel computing.
Professor Leslie Valiant
Harvard University
"Bulk-synchrony: a bridging model for parallel computation"
The success of the Von Neumann model of sequential computation is
attributed to the fact that it is an efficient bridge between software and
hardware. This paper argues that an analogous bridge between software and
hardware is required for parallel computation if it is to become more
widely used, introduces the bulk-synchronous parallel model as a candidate
for this role, and supports the suggestion by giving a number of results
that quantify its efficiency.
Professor Valiant is currently Gordon McKay Professor of Computer Science
and Applied Mathematics at Harvard University. His current research
interests are computational complexity, machine learning, and the theory
of parallel algorithms and architectures. In 1986 he received the
Navanlinna prize for theory of information processing from the
International Mathematical Union.
Mr. Dennis G. Shea
Modular Microsystems Group Manager, IBM T.J.Watson Research Center
"IBM Victor V256"
Victor is a family of partitionable transputer-based multiprocessors that
have been designed at IBM Research to provide researchers with a platform
for experimentation in the area of highly parallel message passing MIMD
machines with distributed memory. Applications running on Victor cover a
variety of scientific and engineering topics such as VLSI waveform
relaxation based circuit simulation and Quantum Monte Carlo simulations
for exploration of high temperature superconductors.
Dennis Shea's research focuses on the design and development of high
performance distributed memory parallel processors and their use in
solving real applications. He is a Ph.D. candidate in the Department of
Computer and Information Science at the University of Pennsylvania, and
has a Master's degree in Computer Systems from Florida Atlantic
University.
H1 TRANSPUTER DISCLOSURE
Ian Pearson, Director of Technology, INMOS
Wednesday afternoon's session will feature a complete technical disclosure
of INMOS' next generation transputer, codenamed H1.
The key features of H1 are a high performance pipelined superscalar
processor and major support for multiprocessing applications. Peak
performance will be more than 150 MIPS and 20 MFLOPS. INMOS, a member of
the SGS-THOMSON Microelectronics group, is the recognized leader in
parallel and multiprocessing, and H1 represents a major advancement in
parallel computing and high speed communications.
The transputer architecture is unique in providing hardware support for
process scheduling and specific instructions for interprocess
communication. As the computational loads on embedded processors
increase, the ability to produce scalable multiprocessor systems is
crucial. H1 represents a significant advance in the transputer's already
proven capabilities in parallel and multiprocessing.
The design goals for H1 were to enhance the transputer's position as the
premier multiprocessing microprocessor, and to establish a new standard in
single processor performance, while maintaining compatibility with
existing transputer products. This session will disclose the means by
which these have been achieved, and time has been scheduled for Mr.
Pearson to field questions from the audience.
Contributed Papers
==================
67 papers have been selected by referees from all over the world. The
choice of papers was based upon their technical quality, the relevance and
originality of the applications described, and their suitability for
presentation at this meeting. A wide range of industrial and academic
organizations will be represented. The papers will be scheduled as either
two or three parallel themed sessions. The successful authors are still
being notified, so a full list of titles and presenters will be posted
shortly. The papers will be published by IOS Press (Amsterdam) in the
series which already contains all the proceedings from the other
Transputer and Occam User Group meetings previously held. A copy of the
proceedings will be given to each delegate upon registration.
Tutorials
=========
The tutorials listed in the timetable below are being provided by
experienced members of the transputer community as an inexpensive
educational service for delegates to TRANSPUTING '91. All will attempt to
provide a practical guide to the topics presented, so that attendees may
rapidly apply the knowledge gained. A complete set of synopses will be
available in the New Year.
Calendar of Events
==================
Monday April 22, 1991
---------------------
Registration
Tutorials on the fundamental principles underlying transputer technologies
and various design paradigms for exploiting them. These tutorials are of
half-day duration unless indicated below.
* Communicating Process Architectures and Transputer Overview
* Designing Parallel - Going Sequential
* Parallelizing Existing Code
* Practical Use of Formal Methods
* Mixed Language Programming on the Transputer
* Logic Programming on the Transputer
* Transputer Programming Environments (full-day)
Evening Reception
Tuesday April 23, 1991
----------------------
Registration
Morning Technical Session - one invited speaker followed by contributed papers
Afternoon Technical Session - contributed papers
Wednesday April 24, 1991
------------------------
Morning Technical Session - contributed papers followed by two invited speakers.
Afternoon - H1 Technical Disclosure
Evening - Conference Dinner with invited speaker
Thursday April 25, 1991
-----------------------
Morning Technical Session - contributed papers followed by one invited speaker.
Afternoon Technical Session - contributed papers
Evening - Awards Dinner
Friday April 26, 1991
---------------------
Full-day workshops on transputer applications and advanced techniques
* Embedded Real-time Control Systems
* Real-time Kernels for C Programmers
* Designing Parallel - a hands-on workshop
* Image Processing - a hands-on workshop
* Scientific Computing
* Office Automation Applications
* Communications Applications
* Artificial Intelligence
* The Helios Operating System - a hands-on workshop
Registration, Accommodation and Travel
======================================
Main conference 23-25 April including 3 nights hotel accommodation $650 US
Main conference 23-25 April without hotel accommodation $450 US
Extra night's lodging booked through Executive Meeting Management $100 US
These hotel rooms have been made available at specially discounted rates
and will sleep up to four occupants.
Student discount - deduct $225 US
Early registration before February 15 1991 - deduct $100 US
(Only one discount allowable per person)
One 1/2 day tutorial/workshop on 22 or 26 April $100 US
Two 1/2 day tutorials/workshops on 22 April $150 US
Full-day tutorials/workshops on 22 or 26 April $150 US
Airfare rates - International airfare rates are available through
American Express +31 20 520 77 77 or Executive Meeting Management (below).
Registration forms will be circulated in the New Year but early
registration is welcome. Forms are available from Executive Meeting
Management (below).
** Enquiries regarding all the above should be directed to **
Brian Raines,
Executive Meeting Management,
PO Box 434,
Camp Hill,
PA 17001
USA
Phone (717) 731 9295
Fax (717) 731 9295 and push * after beep