ENGLE@A.ISI.EDU (11/30/89)
James Price Salsman writes: >> Somewhere else I heard about 6 links ? >Nope, only TWO!!! Kinda defeats the purpose. The H-1 is >definetly going to be a linear array. Given virtual routing, I think you have to ask whether more than two links are necessary. The effect will be that we can all toss out our code that routes between intermediate processors and let the chip handle it. An Inmos representative at NATUG expressed the number of links issue as a dynamic -- you can have more links at the same or slower speeds, or you can have less links at faster speeds. Isn't it also partly due to some clever trick in the chip timing which gives the DMA engines a window to operate without burdening the rest of the chip? I recall that there is some magic number (I think that its 2x) which sets the ratio of the link speed to the CPU such that this window arises (experts care to comment?). As for the MMU, all I would ask for is some form of memory segmentation. In a language such as C where you can set a pointer to an arbitrary integer you need some form process isolation in the memory system. I remember watching errant programs trash video RAM on my Apple II while learning linked lists. If this chip is ever going to make it in some of the more demanding applications we need some way of guarenteeing that you can willfully or accidently overwrite the operating system. I personally can't image using any sort of virtual memory scheme effectively in a transputer array, unless you did the sort of thing that Chrysalis on the BBN Butterfly does. In their system, processes can generate page faults when they attempt to access non-local RAM, which in turn maps the access to somebody else's local RAM. You get the effect of a shared memory machine. In regard to the link speed, one way to get the promised throughput is to just make the links parallel rather than serial. This would give you an eight-fold increase in speed for what I suppose would be an equivalent loss of die area. In larger applications we are also beginning to see a lot of RAM sitting around. Some designers have demanded error correcting memory support and so forth simply because as the amount of RAM increases your changes of errors increase. Does anyone have a feel for whether this should be a concern? How important is upward compatibility? Particularly given the sort of marketplace that the transputer is hitting (primarily innovators and academics). I feel sorry for all those frustrated engineers at Intel who must continue to support this stupid segmented architecture. One thing that RISC has done is its allowed companies with entrenched dinosaur architectures to have an excuse for dropping upward compatibility in their new product line. Its also opened a narrow window for upstarts to jump in and be taken seriously (e.g. MIPS). Are there enough users of the Transputer series to justify maintaining upward compatibility or should (can) Inmos go for the potentially bigger marketplace? Steven W. Engle Senior AI Software Engineer MIMD Systems, Inc.
ADRIAN@vax.oxford.ac.uk (11/30/89)
There seem to be some very confused and peculiar notions of the H1 on this list! The comments made by the INMOS designers at the Edinburgh Occam User Group Meeting in September were very different from most of the recent messages. I thought that a summary had been posted here, or was it only on the Occam list? I know that INMOS are saying very little officially, but maybe someone from Bristol could inject a little real information. I think that it is only the T400 which will have but two links. I believe that the H1 will have *substantially* more! Adrian Lawrence. Oxford University Microprocessor Unit.
lindsay@watnext.Waterloo.EDU (Lindsay Patten) (11/30/89)
In article <[A.ISI.EDU]29-Nov-89.11:26:54.ENGLE>, ENGLE@A.ISI.EDU writes: > Given virtual routing, I think you have to ask whether more than two > links are necessary. The effect will be that we can all toss out our > code that routes between intermediate processors and let the chip > handle it. > Steven W. Engle But two links limits you to a linear array (or loop I guess) which places a definate limitation on the number of processors that you can use for most applications. It makes fault tolerence difficult. It means I can only have a one dimensional hypercube!!! Lindsay Patten Pattern Analysis & Machine Intelligence Group lindsay@watnext Department of Systems Design Engineering lindsay@watnext.waterloo.edu University of Waterloo {utai|decvax|uunet}!watmath!watnext!lindsay
malc@brwo.inmos.co.uk (Malcolm Boffey) (12/01/89)
There seems to be unnecessary confusion over the number of links that the H1 will
have. The processor with 2 links and 2KB is the T400, which you can buy now. The
H1 will have at least 4 links (physical links that is, with unlimited virtual
links mapped onto them). The total bandwidth for all the links together will be
about 80 MBytes/s. Also there will be in the order of 16KB of memory,
configured as cache or conventional on-chip RAM.
Unfortunately I'm not sure what the company's position is on some of the
other things that have been mentions, otherwise I could spend all day posting
news rather than doing any work.
Malcolm Boffey, Transputer Group, Inmos. | Inmos Ltd,
UK: malc@inmos.co.uk | 1000 Aztec West, Almondsbury,
US: malc@inmos.com | Brisol BS12 4SQ.
UUCP: ...uunet!mcvax!ukc!inmos!malc | Tel. +44 454 616616 x610zenith-steven@CS.YALE.EDU (Steven Ericsson Zenith) (05/25/90)
OK. I give up. The cutesy picture is just too tempting a proposition.
As has already been noted, BYTE didn't publish the "Virtual Channel"
article in the USA edition (frankly that's because there really is
perceived to be little interest here in INMOS matters:-( ). But did
you spot the great Linda article in the general section? Can someone
*please* either fax me a copy of the H1 article (203 432-0593), marked
for my attention, or send me a copy by land mail? I'd be ever so
thankfull ... and buy you a beer next time I'm in the UK ;-).
Regards,
Steven
.
Steven Ericsson Zenith * email: zenith@cs.yale.edu
Department of Computer Science | voice: (203) 432 1278
Yale University 51 Prospect Street New Haven CT 06520 USA.
"All can know beauty as beauty only because there is ugliness"cca04@seq1.keele.ac.uk (P.J. Mitchell) (05/25/90)
From article <4181@castle.ed.ac.uk>, by nick@lfcs.ed.ac.uk (Nick Rothwell): > ...and it has a totally inappropriate and rather nausiating "cute" picture > filling half of the first page. It's dreadful isn't it. > Ich weiss jetzt was kein Engel weiss Shouldn't that be "Ich weisse jetzt was ein Engel weissen" ? -- --Paul Mitchell | Computer Centre, JANET: cca04@uk.ac.keele.seq1 | University of Keele, Keele, USENET: cca04@seq1.keele.ac.uk@nss.cs.ucl.ac.uk | Staffordshire, ST5 5BG, U.K. BITNET: cca04%seq1.keele.ac.uk@ukacrl | 0782 - 621111 x 3302
Lydia.Heck@durham.ac.uk (05/26/90)
It might be that it is not:
>> Ich weiss jetzt was kein Engel weiss
but it is CERTAINLY NOT
"Ich weisse jetzt was ein Engel weissen"
as P. Mitchell (cca04@uk.ac.keele.seq1 ) quotes it.
However it could be
" Ich weiss jetzt, was ein Engel weiss "
(To give a translation: I know now what an angel knows )
Lydia.Heck@uk.ac.durhamnick@lfcs.ed.ac.uk (Nick Rothwell) (05/28/90)
In article <emu-pr11.lg.1990.0525.194447.phq7@uk.ac.dur.mts>, Lydia.Heck@durham writes: >It might be that it is not: >>> Ich weiss jetzt was kein Engel weiss >but it is CERTAINLY NOT > >"Ich weisse jetzt was ein Engel weissen" > > >as P. Mitchell (cca04@uk.ac.keele.seq1 ) quotes it. > >However it could be > " Ich weiss jetzt, was ein Engel weiss " >(To give a translation: I know now what an angel knows ) It should translate to "I now know what no angel knows." I thought I'd got it right...? Follow-ups out of comp.sys.transputer into rec.film.wings-of-desire.fan-club. >Lydia.Heck@uk.ac.durham Nick. -- Nick Rothwell, Laboratory for Foundations of Computer Science, Edinburgh. nick@lfcs.ed.ac.uk <Atlantic Ocean>!mcsun!ukc!lfcs!nick ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ Ich weiss jetzt was kein Engel weiss
ken@netcom.UUCP (Ken Kofman) (05/31/90)
I'm new to this newsgroup. I have been hearing vague rumors about a next generation transputer for some time now, and upon logging into this newsgroup I noticed a whole bunch of discussion about the H1. What will the thing do? Of course it will be faster. But will it support static column or fast page DRAM? How much internal memory, or will INMOS switch to a cache? Will there be support for virtual memory? Any additions to the instruction set? Etc. Enquiring minds want to know ken -- Ken Kofman General Nadine: It doesn't matter how it's done, so long as there is a big explosion afterward. Audience: GEEK HIM!!!
J.Wexler@edinburgh.ac.uk (10/05/90)
> Will it really be a 100MIPs, > 100Mb/link processor? > Will those of us who stuck by transputers in the > face of increasingly fast competition be vindicated? 100MIPs: more than 150 claimed, and more than 20 MFLOPS (from tests of early silicon). I think, though, that Inmos are still talking about 100MIPS and 10MFLOPS as realistic speeds for the first generation of these devices that will be marketed. 100Mb/link - Inmos claim 80Mbytes/second total throughput on all four links, which is of the same order as your figure. Vindication: that depends on why you stuck by transputers. It won't be "the fastest chip in the world" in the way that the T800 was (momentarily). It will have slightly better support for operating systems and memory management than the T8, but probably not as much as everybody would like. Inmos refer to this as "an enhanced process model". I doubt whether it will include memory protection and virtual memory support. It will nevertheless be very fast, with a much better balance of processing, transfer and communication-set-up speeds than any other chip, so it will have the edge in large-scale parallelism. It will retain the support for real-time and concurrent systems, still unmatched by other chips. It will still be excellent for embedded systems - but for many such purposes the T2, T4 or T8 will continue to be the best choice, being simpler and cheaper. It will have 16Kbytes of on-chip memory, used by default as a cache but usable directly as RAM if you prefer. The links will not be directly compatible with T-series links (there will be separate chips to interface the two kinds if required). This is because they will offer very important new facilities: multiple channels in each direction supported on a single link (i.e., there will be a firmware multiplexer/demultiplexer), and hardware through-routing so that channels can connect processes on Transputers which are not directly connected. This is achieved by wormhole routing, using a separate chip, which maintains the strict occam model of communication - i.e., termination of transmission implies that the whole message has been received. Thus the typical complement of chips in system using H-series transputers will include Transputers themselves and the new router chips, just as with T-series processors you usually needed C004 switch chips (or equivalent). Single-purpose systems of moderate size may be able to do without the router chips, in the same way that they might not have needed C004s if built with T-transputers. T-to-H link adapter chips are likely to find a lot of uses, (a) in upgrading existing systems, and (b) where it would be wasteful to use H-series chips for all purposes in a system when a T4 or T2 can do many jobs so cheaply. If you just want to use multiple-channels-per-link without through-routing of messages, then the H-series links can do that without any external chips. Personally, I have high hopes of this. As much as anything else, its success depends on Inmos' new openness to giving full support to the languages and systems which potential customers want to use - C and Fortran and so on. John Wexler Edinburgh Parallel Computing Centre _________________________________________________________________________________ Disclaimer: I am not an employee of Inmos, and Inmos has not certified or approved what I have told you. It is fairly old information. It may be inaccurate, misleading, out-of-date, or just plain wrong. I may have remembered some of it wrongly or incompletely. I got it all from (a) published, widely available, sources, and (b) Inmos statements given freely, publicly, and without any request for confidentiality. Neither I nor the University of Edinburgh will be responsible for any use you make of this. No commitment can be assumed for Inmos to deliver any of the specifics that I have described.
kma%nil.utah.edu@cs.utah.edu (Kwan-Liu Ma) (03/19/91)
Hi I need as much information as possible "NOW" about H1, the next generation of Transputer, to talk about the power and potential of Transputer in a report. It will be greatly appreciated if you could tell me everything (in particular performance, exact numbers, etc.) that you know about H1, even through the grapevine. Please send info directly to me. Thanks. Kwan-Liu