davidb@inmos.COM (David Boreham) (03/23/91)
rtm1%salt@bellcore.com (Ravi Masand) writes: >This is a question related to the transputer's >DMA capability. Seems like, when the transputer >gives up the bus (takes MemGranted high) , >it only tristates the 32 address/data bits leaving >the notMemRd, notMemWr3-0 and notMemS0-4 in their >inactive state. Is this correct ? > Yes it is. >This means I have to disconnect them externally >(from the memory system) to allow a device to >perform DMA. > >Anyone know the logic behind this ?? Even the >lowly 68000 and the 8086/88 relenquish the RD/WR >control lines. > Yes. Control lines are not allowed to float because at the transition period between one master and the other, you have no control over the state of the signals. This does not matter in the case of address lines since their state is only of importance at certain times. However, a control line floating low at any time will glitch the memory system and possibly corrupt data. \begin{soapbox} Now you could say ``I'm going to put in pullup resistors, so my control lines will never float low''. Well mabe you can, but it isn't a good idea because resistors with low enough impedence to keep the signals high would burn power in the strobe drivers and slow the strobes down. So, nobody should be designing anything with tristate control lines, control lines should be gated---use a 5ns PAL is you need speed. If the control lines did tristate, the good designers who were using gating, not wired-or would be disadvantaged since they would need extra pullup resistors and all kinds of hassle wondering whether the signals would pickup noise or float around during the handover period. The 68K and 8086 are not wrong. Their busses are not designed to connect directly to memory arrays. In the situation where you either expect your CPU chip to interact with your own DMA controller (which Intel and Moto did) or where you will have a properly specified multimaster bus such as VMEbus, it makes sense to tristate control lines for the benefit of the DMAC-CPU pair. We intended our processors to be used mostly for low chipcount CPU and memory designs and DMA to be used with ``alien'' devices such as network controllers and IMSG300 graphics devices. \end{soapbox} Note that due to some random event in the design process, the IMS T222 and IMST801 memory interface (which is the same circuit), DOES tristate chipselect. Watchout for this one. David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb Bristol, England | (us): uunet!inmos.com!davidb +44 454 616616 ex 547 | Internet: davidb@inmos.com