clif@intelca.UUCP (Clif Purkiser) (10/23/85)
At the request of some people I am reposting a fairly brief description
of the architecture of the 80386.
80386 Product Brief
Introduction
The 80386 is a high performance, 32-bit microprocessor designed for
advanced applications like CAD/CAM engineering workstations, high
resolution graphics, and factory automation. The 80386 brings to
these application an unprecedented performance of 3-4 million
instructions per second, complete 32-bit architecture, and paged
virtual memory support. The iAPX 386 family of products provides the
lastest in microprocessor technology and performance without
compromising compatibility to the large software base of the iAPX 86
family. Of special interest is the 80386's unique virtual machine
capabilities which allow multitasking between diverse operating
systems such as Unix and MS-DOS. This allows OEM's to incorporate
large amounts of standard 16-bit application software directly into
new 32-bit designs.
HIGHLIGHTS
o 32-bit virtual memory microprocessor with 4 gigabytes physical
address space, 4 gigabyte maximum segment size, and 64 terabyte
virtual address space.
o Sustained performance of 3-to-4 million instructions per second
(MIPS)
o Flexible 32-bit architecture with 8-, 16-, 32-bit data types.
o Memory management and protection with segmentation and paging
integrated on-chip.
o 32 entry on-chip paging cache (translation lookaside buffer) with
a 98% hit rate for efficient paging
o Object-code compatible with all iAPX 86 family processors
o Virtual 8086 mode allows direct execution of iAPX 86 family
software and operating systems as guest in a protected 32-bit
environment.
o High speed interface for 80287 and 80387 floating point numeric
coprocessors
o Demultiplexed 32-bit address and data bus with 32 megabyte per
second bandwidth for high speed local buses or local caching
o High speed, high density, CHMOS III technology yields 12 and 16
MHz clock rates
DESCRIPTION
The 80386 rivals the performance of most super minicomputers, at 16
MHz, the 80386 is capable of executing at sustained rates of 3-to-4
million 32-bit instructions per second. This achievement was made
possible through a state-of-the-art design combining advanced
semiconductor technology, a pipelined architecture, address
translation caches, a high performance bus, and specialized,
high-speed coprocessors.
The 80386 32-bit processor provides a rich, generalized register and
instruction set for manipulating 32-bit data and addresses. Advanced
features, such as scaled indexing and a 64-bit barrel shifter, ensure
efficient addressing and fast instruction processing.
For the convenience of compiler writers, the 80386 provides multiple
addressing modes, a capability which ensures that high-level languages
can be implemented in the most efficient manner possible. Scaling by
data type is supported for direct indexing of arrays without the need
to perform math explicitly on an effective address.
The 80386 instruction set is marked by both power and flexibility. It
offers the compiler writer and assembly language programmer a broad
range of choices in which operations and data can be specified.
Special emphasis has been placed on providing optimized instructions
for high-level languages and operating system functions. Programmers
will find that the instruction set is suitable for the entire spectrum
of high-performance computer applications from engineering
workstations through commercial data processing and real-time
control. Instructions are clear, consistent, and quickly learned.
The same highly efficient code is easily generated from source
languages as varied as C, Fortran, Cobol, and Ada*.
Advanced functions, such as hardware-supported multitasking and
virtual memory support, provide the foundation necessary to build the
most sophisticated multitasking and multiuser systems. Many operating
system functions have been placed in hardware to enhance execution
speed. The integrated memory management and protection mechanism
translates virtual addresses to physical addresses and enforces the
protection rules necessary for maintaining task integrity in a
multitasking environment.
The 80386 provides easy access to the large base of software developed
for the 8086, 8088, 80186, 80188, and 80286 microprocessors.
Binary-level-code compatibility allows execution of existing 16-bit
applications without recompilation or reassembly, directly in a
virtual iAPX 86 environment. Programs and even entire operating
systems written for iAPX 86 processors can be run as guests under new
32-bit 80386 operating systems. Since the 80386 memory management
unit is a superset of the 80286's, all 80286 software including
operating systems is directly portable to the 80386. The OEM
preserves his software investment and can reduce the time-to-market
for new products.
PIPELINED MICROARCHITECTURE
The 80386's pipelined architecture performs instruction fetching,
decoding, execution, and memory management functions in parallel.
With this highly parallel operation, instruction fetch and decode
times disappear as consumers of execution time, allowing performance
levels 5 times greater than non-pipelined implementations.
ON-CHIP MEMORY MANAGEMENT AND PROTECTION
The 80386 provides efficent support for memory management and demand
paged virtual memory on-chip. By performing memory management
on-chip, the 386 eliminates the serious access delays inherent in
other implementations that use off-chip memory management units. The
benefit is not only high performance but relaxed memory-access time
requirements, hence lower system cost.
HIGH SPEED BUS
The 80386 has seperate 32-bit data and address paths. A 32-bit access
can be completed in only two clock cycles, enabling the bus to sustain
a throughput of 32 Megabytes per second. By making prompt transfers
between the microprocessor, memory, and peripherals, the high-speed
bus design ensures that the entire system benefits from the
processor's increased performance.
CHMOS III
Intel's advanced CHMOS III process (Complementary High Speed Metal
Oxide Semiconductor) eliminates the frequency and reliability
limitations of traditional CMOS processes and opens a new era in
microprocessor performance. It combines the high performance and high
density capabilities of Intel's leading HMOS III technology with the
low power characteristics of CMOS. Using this technology, the 80386
is designed to operate at 12 and 16 MHz.
NUMERIC COPROCESSOR SUPPORT
The 80287 and 80387 are high-performance floating-point coprocessors
for 80386 designs. A coprocessor takes numerics functions that would
normally be performed in software by the microprocessor and instead
executes them in hardware. The 80287 makes numerics power available
to low-cost 80386 designs, while the 80387 provides enhanced
functionality and the highest numerics performance available for
32-bit microprocessors. Both implement the IEEE 754 floating point
standard, with high-precision 80-bit architectures and full support
for single, double, and extended precision operations. Both
coprocessors offer substantial performance enhancements over numeric
software implementations, are binary-compatible with the
industry-standard 8087 numerics coprocessor, and are fully supported
by Intel and third-party high-level languages.
COPROCESSORS
Most applications can obtain an even higher boost in performance by using
specialized coprocessors. A coprocessor takes functions that would
normally be performed in software by the microprocessor and instead
executes them in hardware. Coprocessors are best viewed as a means of
extending the iAPX 386's already extensive instruction set. Instructions
for the coprocessors are located in-line with code for the processor.
For applications that would benefit from higher precision integer and
floating point calculations, Intel will offer the 80387, a numerics
coprocessor with full support for the IEEE standard for floating-point
operations. The 80387 will run more than six times faster than the 80287,
which has already set new standards in numerics performance, and is
software compatible with its predecessor the 8087. The iAPX 386's
coproccessor interface supports both the 80287 and the 80387 to offer the
system designer the choice of low cost or high performance numeric
solutions.
For word processing and other common applications, system performance will
benefit by using text and graphics coprocessors, and for systems connected
by local area networks, the 82586 and 82588 LAN coprocessors speed
interprocessor communication.
Clif Purkiser
{hplaps quantal amd}!intelca!clifjb@terak.UUCP (John Blalock) (10/29/85)
> At the request of some people I am reposting a fairly brief description > of the architecture of the 80386. > (followed by 197 more lines of advertising) Who are the "some people"? Intel marketing types, no doubt. If everyone feels happy about paying the phone bills to receive your message, I'm sure I can put together a similar "fairly brief description" of my company's latest product which I'll be glad to post. But if I do it, then others will too and the net will become a mass of commercials and then cease to exist. Please register my vote as against such use of the net.
curtis@uwmacc.UUCP (Alan Curtis) (10/31/85)
>> At the request of some people I am reposting a fairly brief description >> of the architecture of the 80386. >> (followed by 197 more lines of advertising) John Blalock writes: >Who are the "some people"? Intel marketing types, no doubt. If everyone feels >happy about paying the phone bills to receive your message, I'm sure I can put >together a similar "fairly brief description" of my company's latest product >which I'll be glad to post. But if I do it, then others will too and the net >will become a mass of commercials and then cease to exist. Please register my >vote as against such use of the net. What newsgroup are we in anyway, net.censor? I read net.micro and net.micro.pc for just the type of information that I got from the postings by the Intel folks. If those people who are reading net.micro are not interested in what seems to me to be a significant step forward in microprocessor development or the fact that the 80386 chip will most likely be the chip of choice for lots, if not most, micro-computer manufacturers in the near future, why the heck are they reading net.micro in the first place? By the way, if the company Mr.Blalock works for comes out with a significant new product that is relevant to this news group, I'd be more than happy to hear about it. _alan
abc@brl-sem.ARPA (Brint Cooper ) (10/31/85)
I read Usenet for professional reasons. It's one more way to try and
keep up with rapidly expanding technology. Therefore, I am happy to receive
such notices as that of the 386 and of other new and innovative
computer products.
If companies are REALLY concerned about their phone bills (and not about
oneupsmanship), they'll immediately direct their host administrators to
shut off net.bizarre, net.jokes, net.women, net.singles, net.social,
net.motss, net.religion.xxx, net.games (except for, perhaps, the game
companies!), net.rec, and the like.
Brint
ARPA: abc@brl.arpa
UUCP: ...{seismo,decvax,cbosgd}!brl-tgr!abc
Dr Brinton Cooper
U.S. Army Ballistic Research Laboratory
Attn: SLCBR-SECAD (Cooper)
Aberdeen Proving Ground, MD 21005-5066
Offc: 301 278-6883 AV: 298-6883 FTS: 939-6883
Home: 301-879-8927Bicer.ES@xerox.arpa (10/31/85)
I don't know what your company does, but if it is as interesting (for the hobbyist/hacker community) as the 386, I'd love to hear about it. Jack Bicer Bicer.ES@XEROX.ARPA
mdm@ecn-pc.UUCP (Mike D McEvoy) (11/01/85)
In article <130@intelca.UUCP> clif@intelca.UUCP (Clif Purkiser) writes: >At the request of some people I am reposting a fairly brief description >of the architecture of the 80386. > > 80386 Product Brief What many of us would like to see is some benchmarks of the 68020 vs 386. May I suggest that you run both th Dhrystone and Whetstone benchmarks ASAP and post them on the net.micro and net.68K. If you need source, let me know. Mike McEvoy 317-497-0509
dfh@scirtp.UUCP (David F. Hinnant) (11/04/85)
> In article <130@intelca.UUCP> clif@intelca.UUCP (Clif Purkiser) writes: > >At the request of some people I am reposting a fairly brief description > >of the architecture of the 80386. > > > > 80386 Product Brief > > What many of us would like to see is some benchmarks of the 68020 vs 386. > May I suggest that you run both th Dhrystone and Whetstone benchmarks ASAP > and post them on the net.micro and net.68K. If you need source, let me know. > > Mike McEvoy I agree, but BEWARE WHO RUNS THE BENCHMARKS! How about an INDEPENDENT UNBIASED volunteer? The Dhrystone should be a better representation than the Whetstone though. Moreover, some highly complex application program (VLSI routing for example) would serve as a good test case. It's important to make sure the operating system doesn't affect the benchmark. Both the CPU and the OS version should be the same (i.e. the same implementation of UNIX). Since I doubt 4.2BSD runs on the 386 yet, how about System III or V? Remember - Benchmark the CPU, not the UNIX implementation. Right Intel? -- David Hinnant SCI Systems, Inc. {decvax, akgua}!mcnc!rti-sel!scirtp!dfh
jabusch@uiucdcsb.CS.UIUC.EDU (11/05/85)
I am interested in seeing/hearing the latest on the market. I am
not so prejudiced as to eliminate Intel. As they are making money at what
they are doing, I can't claim that they're doing everything wrong.
I consider myself open to new ideas, and am not opposed to this
sort of article at all. I see no reason why someone may not post this,
when a good percentage of the last year's articles flamed Intel for one
reason or another. I have read 68k hype from people other than Motorola
reps on this net for quite some time. After this last series of notes
flaming Intel for posting a couple of (relatively) brief articles, I
wonder how many of you who flamed will embarrassed enough that you don't
respond later with 68k or 32k or ... hype.
I say keep the articles brief and informative, and let everyone
do it. Perhaps it might be more appropriate in net.arch, but it's still
interesting.
these are my own opinions.... etc.
John W. Jabusch
U.S. Mail:
Department of Computer Science
University of Illinois at Urbana-Champaign
Room 230 Digital Computer Laboratory
1304 West Springfield Avenue
Urbana, IL 61801
CSNET: jabusch%uiuc@csnet-relay.ARPA
UUCP: {ihnp4,convex,pur-ee}!uiucdcs!jabusch
USENET: ...!{pur-ee,ihnp4}!uiucdcs!jabusch
ARPA: jabusch@uiuc.arpawb6rqn@yojna1.UUCP (Brian Lloyd) (11/08/85)
*** REPLACE THIS LINE WITH YOUR MESSAGE *** Please shut up and let the Intel folk talk. If you don't like what they are saying, exercise your left middle finger (to press the 'd' key, silly). If it is really a problem, someone in the backbone will disconnect the net and we won't have to worry about getting any garbage ever again. In any case, the flame traffic greatly exceeds the original posting and, frankly, I find the flames far more obnoxious. Brian Lloyd ...![bellcore!cp1]!yojna1!wb6rqn