mash@mips.UUCP (John Mashey) (12/20/85)
Henry Spencer writes: > It's noteworthy that Bliss-11, at the time the most heavily optimizing > compiler in the known universe,... > ... did not manage to use more than 3 or 4 registers > effectively on most programs. I'm not aware of any more recent work on > this sort of thing (*sigh*, most likely it's sitting in my To Be Read > pile waiting for me to notice it...), but this augurs ill for the usefulness > of large register sets. Especially since they have to be saved and restored > on function calls and context switches. a) Maybe this is buried in the in-basket: Chow & Hennessy, "Register Allocation by Priority-Based Coloring", Proc, ACM SIGPLAN '84 Symposium on Compiler Construction, SIGPLAN NOTICES 19, 6 (June 84), 222-232. [Also, follow the set of references from this.] Table 3:Of 13 programs, half had substantial gains going from 4 to 6 registers available to the register allocator; going from 6 to 9 registers, 4 of 13 still showed substantial improvement. [this was for PDP-10] b) Remember that such numbers do not include a few others, like function return, subroutine call linkage, stack pointer, etc. c) More registers are more useful in load/store architectures, than in ones like 11's or others with lots of addressing modes for every operation. More registers also happen to be more useful in machines that have 3-operand register-register operations. d) There happen to be a bunch of very interesting things that one can do with a few more registers. [unpublished] ----- Bottom line: figures about PDP-11s don't necessarily prove anything about other architectures; whether something is a good optimization or not depends on numerous factors. > > Actually, I like lots of registers. But when I say "lots", I mean LOTS. > As in RISC machine with overlapping windows, with multiple banks so that > I can do process switches without save/restore. If the register count > doesn't have a "K" on the end, forget it. This may be well and good in TTL RISC designs. Since commercial VLSI RISC chips are yet to be shipped, the verdict is not yet in whether the better tradeoff is a) lots of registers with optimizing compilers, b) big on-chip [and they must be on-chip] register windows. You may have noticed that it is nontrivial to get 1K 32-bit registers on-chip with current technology; even 1.2micron CMOS doesn't do it. Even if you could, is it the right way to spend the silicon? See Dave Patterson's RISC artcile in COMM ACM 28, 1 (Jan 86), p13-14: "Compiler Technology vs Register Windows ... The Berkeley team did not include compiler experts, so a hardware solution was implemented to keep operands in registers..." Since a bunch of VLSI RISCs should appear in 1986, by the end of the year we may have a verdict on the tradeoffs, given current technology. -- -john mashey UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash DDD: 415-960-1200 USPS: MIPS Computer Systems, 1330 Charleston Rd, Mtn View, CA 94043