molik@acsu.buffalo.edu (gregory b molik) (03/17/90)
Does anyone have an implementation of the D-algorithm for determining faults in a logic circuit? Any language is fine. Algorithmic form would also be greatly appreciated. Please send responses to ACSCGBM@ubvms.cc.buffalo.edu OR ACSCGBM@UBVMS.BITNET Greg
chip@chinacat.Lonestar.ORG (Chip Rosenthal) (03/19/90)
molik@acsu.buffalo.edu (gregory b molik) writes: >Does anyone have an implementation of the D-algorithm for determining faults >in a logic circuit? The D-algorithm [Roth67] does not determine faults, it generates a set of test vectors. It is also quite dated, nor is it especially useful for sequential circuits. Some references: Fujiwara, Hideo, "Logic Testing and Design For Testability," The MIT Press, 1985. Timoc, Constantin (ed.), "Selected Reprints on Logic Design for Testability," IEEE Computer Society Press, 1984. Reghbati, Hassan (ed.), "Tutorial: VLSI Testing and Validation Techniques," IEEE Computer Society Press, 1985. Timoc contains a reprint of [Roth67]. Fujiwara presents some more recent modifications and alternatives to the D-algorithm. -- [Roth67] Roth, et. al., "Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits," IEEE Trans. Eleectronic Computers, Oct 1967. -- Chip Rosenthal | Yes, you're a happy man and you're chip@chinacat.Lonestar.ORG | a lucky man, but are you a smart Unicom Systems Development, 512-482-8260 | man? -David Bromberg