William@sri-unix (07/08/82)
Motarola has anounced 68xxx chips planned well into the mid 80's. The 68010, which will support virtual memory by instruction continuation (so that you can read in new pages on the instruction fetch, first operand fetch, AND second operand fetch, if need be) will be sampled towards the end of this year or early 83. The 68010 is Pin and software compatable with the 68000. It also includes relocateable interupt vector tables and instructions to move data in between (for example) user and system address spaces. Going downwards, the 68008 will be available about the same, and features an 8 bit bus and a 48 pin package, with 60% of the preformnance of the 68000. Going upwards, they have the 68020 and the 68881. The 68000 is a full 32 bit CPU with a 32 bit data path, a 32 bit address path, on chip instruction cache and a co-processor interface that can handle up to 8 or 16 co-processors. The 68881 is a floating point co-processor that works with this interface. It will handle all the IEEE formats and functions, and can be used as an IO device with earlier model 68xx(x) processors. All the processors are upward object code compatable with the 68000. Motarola is definitely trying to say "The 68000 architecture is good, and we are going to continue to improve and expand upon it, so that if you commit yourself to our chips, you wont be sorry..." Ive attended a bunch of free motarola seminars recently, and can probably provide more detailed information if anyone is interested. Bill Westfield