leff@smu.UUCP (Laurence Leff) (07/06/89)
9th International Symposium on Computer Hardware Description Languages and their Applications CHDL-89 Proceedings Available The 9th IFIP Symposium on Computer Hardware Description Languages, CHDL-89, took place last week in Washington, D.C. The trade edition of the proceedings will be published by North-Holland bui it will be a few months before it is commercially available. There are a limited number of extra copies of the participants edition (soft cover). If you are interested in obtaining a copy of the proceedings, you can save time and money by ordering one of these copies from: Dr. William H. Joyner IBM, T.J. Watson Research Center P.O. Box 218 Yorktown Heights N.Y. 10598 Telephone: (914) 945-1059 Internet: joyner@ibm.com Cost is $25.00 (includes postage and handling) Table of Contents: ------------------------------------------------------------------------ Session: DESIGN LANGUAGES EXEL: A Language for Interactive Behavioral Synthesis, N.D. Dutt, D.D. Gajski, USA ODICE: Object-Oriented Hardware Description in CAD Environment, W. Muller, F.J. Rammig, FRG Computer Architecture Specification with Interval Temporal Logic, P.A. Wilsey, USA ------------------------------------------------------------------------ Session: SYNTHESIS I Design Representation for the Synthesis of Behavioral VHDL Models, R. Camposano, R.M. Tabet, USA SYS: A CHDL-Based Systolic Synthesis System, R. Hartenstein, K. Lemmert, FRG Constraint Description and Extraction in RASP, D. Baldwin, USA ------------------------------------------------------------------------ Session: VERIFICATION I Functional Semantics of Microprocessors at the Machine Instruction Level, J.L. Paillet, France Timing Constraints: Formalizing their Description and Verification, G.J. Milne, Scotland Specification and Verification of Pipelined Hardware in HOP, G.C. Gopalakrishnan, Canada ------------------------------------------------------------------------ Session: DESIGN SYSTEMS Experience with Simulation Tools in the Design Process of High Performance General Purpose Computers, K. Ebner, FRG Modeling Digital Systems in an Integrated Design Environment, L.G. Goldenziner, F.R. Wagner, C.M. Dal Sasso-Freitas, Brazil Integration of a CHDL into an Engineering Environment, J. Miller, J. Strauss, F. Rammig, FRG ------------------------------------------------------------------------ Session: SYNTHESIS II Synthesizing Correct Sequential Circuits, G.M. Brown, M.E. Leeser, USA Modular Implementation of Finite State Machines Observing Topological Constraints, W. Grass, M. Mutz, FRG Cycle Level Timing Constraints in Behavioral Hardware Descriptions, V. Berstis, USA ------------------------------------------------------------------------ Session: HIGH-LEVEL DESIGN Functional and Operational Specifications of Computer Architectures, P.A. Wilsey, S. Dasgupta, USA Knowledge-Based Assistance for the Description of Computer Architectures, B. Scherf, FRG A Derived Garbage Collector, C.D. Boyer, S.D. Johnson, USA ------------------------------------------------------------------------ Session: VERIFICATION II Design Verification of Sequential Machines Based on E-Free Regular Temporal Logic, H. Hiraishi, USA Specification, Verification, and Synthesis of Control Circuits with Propositional Temporal Logic, M. Fujita, H. Fujisawa, Japan A Language for Compositional Specification and Verification of Finite State Hardware Controllers, E.M. Clarke, D.E. Long, K.L. McMillan, USA ------------------------------------------------------------------------ Session: VHDL APPLICATIONS A High Performance VHDL Simulator with Integrated Switch and Primitive Modeling, S.P. Smith, J. Larson, USA Using VHDL as a Synthesis Language in the Honeywell VSYNTH System, P. Harper, S. Krolikoski, O Levia, USA Using VHDL as a Language for Synthesis of CMOS VLSI Circuits, S.P. Levitan, A.R. Martello, R.M. Owens, M.J. Irwin, USA BTG: A Behavioral Test Generator, M.D. O'Neill, D.D. Jani, C.H. Cho, J.R. Armstrong, USA ------------------------------------------------------------------------ -- ------------------------------------------------------------------------ Mario R. Barbacci, arpanet: mrb@sei.cmu.edu uunet: ...!harvard!sei.cmu.edu!mrb Software Engineering Institute, CMU, Pittsburgh PA 15213, (412) 268-7704