rdt@houxk.UUCP (R.TRAUBEN) (05/12/85)
Hello:
Motorola claims 45 nanoseconds for 68851 translation time on the new
paged mmu (mos vlsi version. NOT either the ttl mini-board gate
array version or its' unsuccessful parent, the 68451).
Does anyone know how they are defining the translation time parameter?
Measured from what event (as a starting reference) to what event
(as an ending point)?
Virtual address valid to Physical address valid?
Virtual address Strobe valid to Physical address valid?
Virtual address Strobe valid to Physical address STROBE valid?
Does the Translation end point include the time to do access rights checking?
Will the MMU be constrained to run off the same clock as the CPU
to achieve this fast access time?
Any help is appreciated. I'm confused on what 45ns really means.
Thanks,
> Richard
P.S. Address out times alone on 68xxx (*MOS) parts are in the vicinity
of 30 nanoseconds!davet@oakhill.UUCP (Dave Trissel) (05/13/85)
In article <428@houxk.UUCP> rdt@houxk.UUCP (R.TRAUBEN) writes: >Hello: > >Motorola claims 45 nanoseconds for 68851 translation time on the new >paged mmu (mos vlsi version. NOT either the ttl mini-board gate >array version or its' unsuccessful parent, the 68451). > >Any help is appreciated. I'm confused on what 45ns really means. > Sorry, but unless you have a non-disclosure agreement that information should not be given to you. (If you do then you should already have such information.) You can contact your local Motorola sales office to arrange for signing a non-disclosure agreement. I can say that both the gate-array and the MC68851 versions support 1 cycle translations and 0 cycle translations are possible for very fast logical caches. Motorola Semiconductor Inc. Dave Trissel Austin, Texas {ihnp4,seismo,gatech}!ut-sally!oakhill!davet