hascall@atanasoff.cs.iastate.edu (John Hascall) (01/31/89)
In response to someone proposing adding instructions to a RISC machine, I wrote: >> Here it is again, adding instructions to a RISC machine... won't >> be long before we have a RISC machine with more instructions >> than a VAX.... :-) And was "corrected" by someone* thusly: > And again... > Sigh, RISC doesn't mean a small number of instructions. RISC means.... REDUCED Instruction Set Computer (i.e., a reduced number of instructions) True, many RISC machine incorporate a number of other feature, which because they have been used by a number of RISC machines, have come to considered a part of RISC--but there is no reason that these feature could not be part of a CISC machine (other than chip real-estate). I think the real problem here is a poorly named acronym, but it probably sounded "cute" (I, for one, am quite tired of papers titled "A RISCy blah blah blah" etc). Perhaps we could have a new buzzword contest, how about SOC (simple, orthogonal computer)? My $.02 (or less) worth, John Hascall ISU Comp Center * My apologies for losing the attribution above, but rn barfed on the overly long "References:" field and I had to do this by hand.
diamond@csl.sony.JUNET (Norman Diamond) (01/31/89)
In article <747@atanasoff.cs.iastate.edu>, hascall@atanasoff.cs.iastate.edu (John Hascall) writes: > > Sigh, RISC doesn't mean a small number of instructions. RISC means.... > REDUCED Instruction Set Computer (i.e., a reduced number of instructions) Maybe reduced number of KINDS of instructions. If you have an add instruction for a byte and another for a word ... if you have an add instruction for signed and another for unsigned ... do you think these are ciscy? Having an add instruction for a little-endian word and another for a big-endian word strikes me as a little silly (maybe a big silly :-), but still riscy. Incidentally, wouldn't little-beginnian and big-beginnian be more accurate? -- Norman Diamond, Sony Computer Science Lab (diamond%csl.sony.jp@relay.cs.net) The above opinions are my own. | Why are programmers criticized for If they're also your opinions, | re-inventing the wheel, when car you're infringing my copyright. | manufacturers are praised for it?
rodman@mfci.UUCP (Paul Rodman) (02/01/89)
In article <747@atanasoff.cs.iastate.edu> hascall@atanasoff.cs.iastate.edu (John Hascall) writes: > > In response to someone proposing adding instructions to a RISC > machine, I wrote: > >>> Here it is again, adding instructions to a RISC machine... won't >>> be long before we have a RISC machine with more instructions >>> than a VAX.... :-) > > And was "corrected" by someone* thusly: > >> And again... >> Sigh, RISC doesn't mean a small number of instructions. RISC means.... > > REDUCED Instruction Set Computer (i.e., a reduced number of instructions) At the risk of starting more pointless RISC/CISC flameage, let me add my 2 cents worth here: (I know many of you out there won't agree....:-) The term RISC has been terribly misused, but my personal definition has be widened to include machines that don't have a "small" number of instructions. E.g. the Multiflow Trace,( which I am using to compose this mail) has a VERY large space of possible instructions. I would still term this machine RISCy as each functional unit is controlled directly by the instruction word, and is decoupled from instruction packets that are wired to other functional units. Hence the original purpose of the RISC idea is served. Conventional RISCs are designed to approach 1 "op" per cycle. We designed a multiple-functional unit machine that executes >1 ops / cycle. The VLIW compiler is considerably "smarter" than a typical RISC compiler, and the compiler <-> hardware fusion is even more important than for a simple RISC, but the basic mind set is still the same. Paul K. Rodman rodman@mfci.uucp