mfreeman@cascade.Stanford.EDU (Martin Freeman) (06/05/91)
Just When You Thought It Was Safe To Go On Vacation:
HOT CHIPS SYMPOSIUM III
A Symposium on High-Performance Chips
(Advance Program)
Sponsored by the IEEE Computer Society
Technical Committee on Microprocessors
Stanford University, Palo, Alto, California
August 26-27, 1991
Attend HOT Chips III, a symposium on high-performance chips, which will bring
together researchers and developers of chips used to construct high-performance
workstations and systems. Enjoy the informal format offering interaction with
speakers. This first two HOT Chips Symposiums were huge successes and prompted
articles in three special issues of IEEE Micro magazine. This year's HOT Chips
III will again bring you the latest developments in chip technology.
ORGANIZING COMMITTEE
General Chairman: Martin Freeman, Philips Research
Program Co-Chairmen: Forest Baskett, Silicon Graphics
John Hennessy, Stanford University
Finance Chairman: Hasan AlKhatib, Santa Clara University
Registration Chairman: Robert Stewart, Stewart Research
Publication Chairman: Nam Ling, Santa Clara University
Publicity Chairman: Andrew Goforth, NASA Ames Research Center
Local Arrangements Chairman: Robert Stewart, Stewart Research
PROGRAM COMMITTEE
Forest Baskett, Silicon Graphics (Program Co-Chair)
John Crawford, Intel
David Ditzel, Sun Microsystems
John Hennessy, Stanford University (Program Co-Chair)
John Mashey, MIPS Computer Systems
Teresa Meng, Stanford University
Alan Smith, U.C. Berkeley
PROGRAM
August 26, 1991 - Dinkelspiel Auditorium
7:30 - 8:30 Onsite Registration
8:30 - 8:45 Welcome and Opening Remarks
Martin Freeman, General Chair
Forest Baskett and John Hennessy, Program Co-Chairs
8:45 - 10:15 High-Performance Processors - I
. Viking: A Superscalar SPARC Processor
Greg Blanck, Sun Microsystems &
Steve Krueger, Texas Instruments
. R4000 Technical Overview
Tom Riordan, MIPS Computer Systems
. High-Performance PA-RISC Processor for "Snakes" Workstation
Mark Forsyth, Charles Kohlhardt, &
Ruby Lee, Hewlett Packard
10:15 - 10:45 BREAK
10:45 - 12:15 Highly Parallel Chips
. The LIFE Family of High-Performance Single Chip VLIWs
Gerrit Slavenburg, Philips Research Palo Alto
. The Message-Driven Processor
William Dally, J. Stewart Fiske, Waldemar Horwat,
John Keen, Richard Lethin, Michael Noakes, & Peter Nuth
MIT Artificial Intelligence Laboratory
D. Scott Wills
University of Central Florida
Andrew Chien
University of Illinois
Salim Ahmed, Paul Carrick, Roy Davison, Greg Fyler,
Steve Lear, Mark Vestrich, & Ted Nguyen
Intel
. The TRW CPUAX Superchip: A 4.1 Million Transistor CMOS CPU
A. Miscione, R. Almeida, H. Hennecke, & R. Mann
TRW Micro Electronics
12:15 - 1:45 LUNCH
1:45 - 3:15 High-Performance Processors - II
. An 80 MHz 64-Bit Floating Point RISC Processor with
Direct DRAM Support
James Hesson, Micron Technology
. The 80860XP: 2nd Generation of the i860(tm) RISC
Processor Family
David Perlmutter & Michael Kagan, Intel Israel
. Beyond Claims of Free Transistors and Abundant
Instruction-Level Parallelism
Michael Smith, Stanford University
3:15 - 3:45 BREAK
3:45 - 5:15 Low Power and Low Cost
. SPARC System Chipset
Greg Favor, Tera Microsystems
. The SparKIT Chipset: How to Clone a Sparcstation
Mohammed Wasfi, LSI Logic Corporation
. SMM, The "Virtual 386(tm)"
Dave Vannier, Intel
5:15 - 7:15 RECEPTION
7:30 EVENING PANEL SESSION: "Five Instructions Per Clock:
Truth or Consequences"
Alan Smith, U.C. Berkeley
John Mashey, MIPS Computer Systems
August 27, 1991 - Dinkelspiel Auditorium
8:00 - 9:00 Onsite Registration
9:00 - 10:30 Communications
. A GaAs 200 Mbps 64x64 Crosspoint Chip
Ron Cates, Vitesse Semiconductor
. RN1: Low-Latency, Dilated, Crossbar Router
Henry Minsky, Tom Knight, Andre' DeHon
. The NEURON Chip Family Architecture
Robert Dolin, Echelon
. The Protocol Engine Chipset
Greg Chesson, Silicon Graphics
10:30 - 11:00 BREAK
11:00 - 12:30 Caches and Floating Point
. R4000 Cache Design Tradeoffs and Performance
Earl Killian, MIPS Computer Systems
. The Megacell Differentiated Floating Point Product Family
Merrick Darley, Don Steiss, Peter Groves, David Bural,
Maria Gill, & Tod Wolf
Texas Instruments
. High-Integration 2nd Level Cache for the i486 CPU
Adi Gobert, Intel Corporation
12:30 - 2:00 LUNCH
2:00 - 3:30 Special Processors
. C-Cube CL950 MPEG Video Decoder/Processor
Stephen Purcell, C-Cube Microsystems
. A Smart Frame Buffer
Joel McCormack, DEC Western Research Laboratory
. A High-Performance, Low-Cost Neural Chip
Gary Tahara, Inova Microelectronics
3:30 - 4:00 BREAK
4:00 - 5:30 High-Performance Processors - III
. National's Swordfish - A Superscalar with DSP
Reuven Marko & Motti Beck, National Semiconductor
. H1: A Superscalar Pipelined CPU
Bob Krysiak, Richard Forsythe & Roger Sheperd
INMOS Ltd.
. The Pinnacle SPARC Module
Raju Vegeshna, Ross Technology
5:30 Closing Remarks
HOUSING INFORMATION
Housing is available on the Stanford University campus in Stern Hall, a short
walk from Dinkelspiel Auditorium where the symposium will be held. Housing
is in student residences with central lavatory facilities and costs $40 per
night. A key deposit is required that will be refunded at checkout. Housing
arrangements on the Stanford campus must be mase by July 26.
Housing is also available at numerous hotels and motels on the peninsula in
Palo Alto, Menlo Park, Mountain View, and Los Altos close to Stanford
University.
If you would like additional housing information, please check the housing
information request box on the registration form.
QUESTIONS?
For more information on registration and local arrangements contact Dr. Robert
Stewart at (415) 941-6699 or r.stewart@compmail.com (use email after
June 1).
REGISTRATION FEES
Postmarked by Subsequent
July 26 Registration
IEEE Computer Society $170 $240
or ACM Member
Non-Member $240 $290
Full-Time Student $75 $100
Instead of payment by check, registration may be charged to VISA or MasterCard.
Registration charged to a credit card may be FAXed to Dr. Robert Stewart at
(415) 941-6699.
REGISTRATION INCLUDES
* Attendance * Sunday evening wine & cheese reception
* One copy of the notes * Monday evening reception
* Two luncheons * Coffee breaks
* Parking at Florence Moore Hall
On-site registration is available Sunday evening at the wine and cheese
reception, and each morning at the symposium.
WINE & CHEESE RECEPTION
* Sunday, August 25 --- 5:00-7:00 PM
* Rodin Gardens, Stanford University
* A guided tour of the statuary will be provided.
=============================================================================
HOT CHIPS III REGISTRATION FORM
Name________________________________________________________________________
Affiliation_________________________________________________________________
Address_____________________________________________________________________
City/State/Zip______________________________________________________________
Country_____________________________________________________________________
Area Code/Phone #___________________________________________________________
Email Address_______________________________________________________________
Membership: IEEE______ ACM_______
Membership Number___________________________________________________________
Check One:
______Check drawn on a U.S. Bank ______MasterCard
Make Check Payable To:
Hot Chips Symposium ______VISA
Name on Credit Card_________________________________________________________
Credit Card #_______________________________________________________________
Expiration Date_____________________________________________________________
Signature___________________________________________________________________
Amount Enclosed_____________________________________________________________
Mail To:
Dr. Robert G. Stewart
Stewart Research Enterprises
1658 Belvoir Drive
Los Altos, CA 94024
______Housing Information Requested